Searched refs:OUT_PKT4 (Results 1 - 25 of 45) sorted by relevance

12

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_screen.h43 OUT_PKT4(ring, reg, 1);
H A Dfd5_emit.c309 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
474 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
479 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
488 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
496 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
519 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
537 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
540 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
557 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
566 OUT_PKT4(rin
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H A Dfd5_compute.c96 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
99 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 1);
104 OUT_PKT4(ring, REG_A5XX_SP_CS_CTRL_REG0, 1);
111 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
116 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1);
120 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
126 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
130 OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2);
133 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
140 OUT_PKT4(rin
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H A Dfd5_gmem.c100 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
116 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
125 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
153 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
164 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
167 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
173 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
177 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
180 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
185 OUT_PKT4(rin
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H A Dfd5_draw.c55 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
207 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
210 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
213 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
217 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
220 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
223 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
226 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
234 OUT_PKT4(rin
[all...]
H A Dfd5_program.c366 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
383 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
386 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
398 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
415 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
418 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
422 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
426 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
430 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
434 OUT_PKT4(rin
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H A Dfd5_blitter.c162 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
165 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
170 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
173 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
176 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2100, 1);
179 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2180, 1);
182 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1);
185 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
188 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
191 OUT_PKT4(rin
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H A Dfd5_emit.h108 OUT_PKT4(ring, REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO, 5);
162 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
169 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1);
181 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
187 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_emit.c335 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
501 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
506 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
518 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
527 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
550 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
568 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
571 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
588 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
597 OUT_PKT4(rin
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H A Dfd5_screen.h45 OUT_PKT4(ring, reg, 1);
H A Dfd5_gmem.c100 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
119 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
128 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
155 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
166 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
169 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
175 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
179 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
182 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
187 OUT_PKT4(rin
[all...]
H A Dfd5_draw.c54 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
179 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
182 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
185 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
191 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
194 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
197 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
200 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
208 OUT_PKT4(rin
[all...]
H A Dfd5_compute.c49 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
52 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 1);
57 OUT_PKT4(ring, REG_A5XX_SP_CS_CTRL_REG0, 1);
65 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
70 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1);
74 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
81 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
85 OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2);
88 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
96 OUT_PKT4(rin
[all...]
H A Dfd5_program.c298 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
315 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
318 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
335 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
352 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
355 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
359 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
363 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
367 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
371 OUT_PKT4(rin
[all...]
H A Dfd5_emit.h115 OUT_PKT4(ring, REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO, 5);
176 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
183 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1);
195 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
200 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_rasterizer.c110 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8000, 1);
112 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8001, 1);
114 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8004, 1);
117 OUT_PKT4(ring, REG_A6XX_GRAS_SU_CNTL, 1);
120 OUT_PKT4(ring, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
124 OUT_PKT4(ring, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
130 OUT_PKT4(ring, REG_A6XX_PC_RASTER_CNTL, 1);
133 OUT_PKT4(ring, REG_A6XX_GRAS_CL_CNTL, 1);
H A Dfd6_gmem.c108 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
116 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
121 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
133 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
136 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
139 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
149 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
179 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
186 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
189 OUT_PKT4(rin
[all...]
H A Dfd6_zsa.c128 OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
131 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
134 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
137 OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
144 OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
147 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
150 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
153 OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
H A Dfd6_program.c364 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
371 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
374 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
378 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
382 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
385 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
389 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
392 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
395 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
398 OUT_PKT4(rin
[all...]
H A Dfd6_emit.c338 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
443 OUT_PKT4(ring, tex_samp_reg, 2);
539 OUT_PKT4(ring, tex_const_reg, 2);
545 OUT_PKT4(ring, tex_count_reg, 1);
659 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 4);
664 OUT_PKT4(ring, REG_A6XX_VFD_DECODE(j), 2);
673 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(j), 1);
681 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
706 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
709 OUT_PKT4(rin
[all...]
H A Dfd6_compute.c79 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
83 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
87 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
94 OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
101 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
108 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
115 OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
167 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
179 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
H A Dfd6_draw.c212 OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
216 OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
276 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
279 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
287 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
290 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
305 OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
308 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
312 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
319 OUT_PKT4(rin
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_program.c126 OUT_PKT4(ring, instrlen, 1);
129 OUT_PKT4(ring, first_exec_offset, 7);
143 OUT_PKT4(ring, hw_stack_offset, 1);
287 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
299 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
303 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
309 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
316 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
323 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
330 OUT_PKT4(rin
[all...]
H A Dfd6_compute.c53 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
57 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
65 OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
74 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
79 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, 1);
89 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
98 OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 2);
107 OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
157 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
172 OUT_PKT4(rin
[all...]
/xsrc/external/mit/MesaLib/dist/src/freedreno/computerator/
H A Da6xx.c121 OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
124 OUT_PKT4(ring, REG_A6XX_SP_PERFCTR_ENABLE, 1);
127 OUT_PKT4(ring, REG_A6XX_SP_FLOAT_CNTL, 1);
130 OUT_PKT4(ring, REG_A6XX_HLSQ_INVALIDATE_CMD, 1);
139 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL, 1);
143 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
150 OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
158 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
166 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
174 OUT_PKT4(rin
[all...]

Completed in 93 milliseconds

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