Searched refs:RADEON_PPLL_DIV_0 (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h977 #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h977 #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ macro
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dlegacy_output.c207 ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel);
H A Dradeon_driver.c1085 n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
1091 switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
H A Dradeon_reg.h1459 #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ macro
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dradeon_reg.h1459 #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ macro

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