Searched refs:cs_array (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_cs.c641 struct radeon_cmdbuf **cs_array,
676 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
677 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
688 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
723 cs = (struct radv_amdgpu_cs*)cs_array[i];
821 struct radeon_cmdbuf **cs_array,
830 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
837 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
845 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
859 r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_coun
640 radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys * ws,struct radeon_cmdbuf ** cs_array,unsigned count,struct radv_amdgpu_winsys_bo ** extra_bo_array,unsigned num_extra_bo,struct radeon_cmdbuf * extra_cs,const struct radv_winsys_bo_list * radv_bo_list,uint32_t * bo_list) argument
817 radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
907 radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
994 radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
1195 radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * bo_list,bool can_patch,struct radeon_winsys_fence * _fence) argument
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_cs.c662 radv_amdgpu_get_bo_list(struct radv_amdgpu_winsys *ws, struct radeon_cmdbuf **cs_array, argument
682 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers && !ws->global_bo_list.count) {
683 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)cs_array[0];
697 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)cs_array[i];
727 cs = (struct radv_amdgpu_cs *)cs_array[i];
806 struct radeon_cmdbuf **cs_array, unsigned cs_count,
810 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
820 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
828 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
844 result = radv_amdgpu_get_bo_list(cs0->ws, cs_array, cs_coun
804 radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs) argument
882 radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs) argument
960 radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs) argument
1149 radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radv_winsys_sem_info * sem_info,bool can_patch) argument
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h281 struct radeon_cmdbuf **cs_array,
H A Dradv_device.c2952 struct radeon_cmdbuf **cs_array; local in function:radv_QueueSubmit
2985 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2993 cs_array[j] = cmd_buffer->cs;
3018 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3032 radv_check_gpu_hangs(queue, cs_array[j]);
3040 free(cs_array);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h277 struct radeon_cmdbuf **cs_array, unsigned cs_count,
H A Dradv_device.c4735 struct radeon_cmdbuf **cs_array = local in function:radv_queue_submit_deferred
4742 cs_array[j] = cmd_buffer->cs;
4760 result = queue->device->ws->cs_submit(ctx, queue->vk.index_in_family, cs_array + j, advance,
4764 free(cs_array);
4769 radv_check_gpu_hangs(queue, cs_array[j]);
4777 free(cs_array);

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