Searched refs:physReg (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_assembler.cpp69 if (instr->operands[3 + i].physReg() != instr->operands[3].physReg().advance(i * 4))
114 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0;
115 encoding |= instr->operands.size() >= 2 ? instr->operands[1].physReg() << 8 : 0;
116 encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0;
139 encoding |= !instr->definitions.empty() && !(instr->definitions[0].physReg() == scc)
140 ? instr->definitions[0].physReg() << 16
141 : !instr->operands.empty() && instr->operands[0].physReg() <= 127
142 ? instr->operands[0].physReg() << 16
154 encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 1
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H A Daco_lower_to_hw_instr.cpp509 vcndmask_identity[i], Operand(PhysReg{src.physReg() + i}, v1),
588 bld.readlane(Definition(PhysReg{dst.physReg() + i}, s1), Operand(PhysReg{tmp + i}, v1),
591 emit_op(ctx, tmp, dst.physReg(), tmp, vtmp, reduce_op, src.size());
625 bld.readlane(Definition(PhysReg{dst.physReg() + i}, s1), Operand(PhysReg{tmp + i}, v1),
628 emit_op(ctx, tmp, dst.physReg(), tmp, vtmp, reduce_op, src.size());
723 identity[i].physReg() == PhysReg{sitmp + i});
816 emit_op(ctx, dst.physReg(), tmp, vtmp, PhysReg{0}, reduce_op, src.size());
829 bld.readlane(Definition(PhysReg{dst.physReg() + k}, s1), Operand(PhysReg{tmp + k}, v1),
832 } else if (dst.physReg() != tmp) {
834 bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg{dst.physReg()
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H A Daco_optimizer_postRA.cpp91 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255);
92 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256);
95 unsigned r = def.physReg().reg();
109 last_writer_idx(pr_opt_ctx& ctx, PhysReg physReg, RegClass rc) argument
112 assert(physReg.reg() < max_reg_cnt);
113 Idx instr_idx = ctx.instr_idx_by_regs[ctx.current_block->index][physReg.reg()];
115 unsigned r = physReg.reg();
130 assert(op.physReg().reg() < max_reg_cnt);
131 Idx instr_idx = ctx.instr_idx_by_regs[ctx.current_block->index][op.physReg().reg()];
135 instr_idx = last_writer_idx(ctx, op.physReg(), o
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H A Daco_insert_NOPs.cpp214 if (regs_intersect(reg, mask_size, def.physReg(), def.size())) {
215 unsigned start = def.physReg() > reg ? def.physReg() - reg : 0;
276 state, state.block, min_states, op.physReg(), u_bit_consecutive(0, op.size()), false);
337 test_bitset_range(ctx.smem_clause_write, op.physReg(), op.size())) {
344 if (!*NOPs && test_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size()))
400 if (op.physReg() == vccz)
402 if (op.physReg() == execz)
414 NOPs = MAX2(NOPs, ctx.vmem_store_then_wr_data[(def.physReg() & 0xff) + i]);
493 set_bitset_range(ctx.smem_clause_read_write, op.physReg(), o
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H A Daco_ssa_elimination.cpp66 if (phi->operands[i].physReg() == phi->definitions[0].physReg())
152 if (ignore_exec_writes && instr->definitions[i].physReg() == exec)
154 if (instr->definitions[i].physReg() != instr->operands[i].physReg())
160 if (ignore_exec_writes && instr->definitions[0].physReg() == exec)
292 if (def.physReg() == exec || def.physReg() == exec_hi)
312 copy_to_exec |= successor_phi_info.def.physReg() == exec;
313 copy_from_exec |= successor_phi_info.op.physReg()
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H A Daco_register_allocation.cpp58 reg = def.physReg();
305 fill_subdword(op.physReg(), op.bytes(), op.tempId());
307 fill(op.physReg(), op.size(), op.tempId());
310 void clear(Operand op) { clear(op.physReg(), op.regClass()); }
315 fill_subdword(def.physReg(), def.bytes(), def.tempId());
317 fill(def.physReg(), def.size(), def.tempId());
320 void clear(Definition def) { clear(def.physReg(), def.regClass()); }
745 def.setFixed(it->second.physReg());
747 ctx.assignments[def.tempId()].reg = def.physReg();
761 other.second.setFixed(it->second.physReg());
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H A Daco_validate.cpp163 check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
195 check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
199 check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
485 instr->definitions[1].physReg() == scc,
596 check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
724 unsigned byte = op.physReg().byte();
781 unsigned byte = def.physReg().byte();
886 if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
891 op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) ||
893 op.physReg()
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H A Daco_opt_value_numbering.cpp140 if (a->operands[i].physReg() != b->operands[i].physReg())
142 if (a->operands[i].physReg() == exec && a->pass_flags != b->pass_flags)
156 if (a->definitions[i].physReg() != b->definitions[i].physReg())
158 if (a->definitions[i].physReg() == exec)
H A Daco_live_var_analysis.cpp121 if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc)
150 if (operand.isFixed() && operand.physReg() == vcc)
187 assert(insn->definitions[0].isFixed() && insn->definitions[0].physReg() == exec);
192 if ((definition.isFixed() || definition.hasHint()) && definition.physReg() == vcc)
243 if (operand.isFixed() && operand.physReg() == vcc)
H A Daco_insert_waitcnt.cpp254 PhysReg reg{op.physReg() + j};
266 PhysReg reg{def.physReg() + j};
294 instr->definitions[0].physReg() == sgpr_null) {
599 insert_wait_entry(ctx, op.physReg(), op.regClass(), event, false, has_sampler);
605 insert_wait_entry(ctx, def.physReg(), def.regClass(), event, true, has_sampler);
H A Daco_print_ir.cpp167 print_constant(operand->physReg().reg(), output);
185 print_physReg(operand->physReg(), operand->bytes(), output, flags);
206 print_physReg(definition->physReg(), definition->bytes(), output, flags);
618 offset += instr->definitions[0].physReg().byte();
632 offset += instr->operands[i].physReg().byte();
H A Daco_statistics.cpp314 deps_available = MAX2(deps_available, reg_available[op.physReg().reg() + i]);
399 int32_t* available = &reg_available[def.physReg().reg()];
481 blocks[0].reg_available[def.physReg().reg() + i] = vs_input_latency;
H A Daco_ir.h750 constexpr PhysReg physReg() const noexcept { return reg_; } function in class:aco::Operand
839 if (isFixed() && other.isFixed() && physReg() != other.physReg())
844 return other.isConstant() && other.physReg() == physReg();
925 constexpr PhysReg physReg() const noexcept { return reg_; } function in class:aco::Definition
1015 if (op.isFixed() && op.physReg() == exec)
H A Daco_ir.cpp309 instr->definitions.back().physReg() != vcc)
312 if (!pre_ra && instr->operands.size() >= 3 && instr->operands[2].physReg() != vcc)
H A Daco_lower_to_cssa.cpp112 assert(op.isFixed() && op.physReg() == exec);
H A Daco_spill.cpp198 if (op.isFixed() && op.physReg() == exec)
408 if (op.isFixed() && op.physReg() == exec)
1027 assert(phi->definitions[0].isFixed() && phi->definitions[0].physReg() == exec);
H A Daco_optimizer.cpp785 return op.isFixed() && op.physReg() == exec;
2056 if (!instr->operands[0].isFixed() || instr->operands[0].physReg() != exec)
3614 pred_instr->definitions[1].physReg() == scc);
3772 instr->operands[0].isFixed() && instr->operands[0].physReg() == scc) {
H A Daco_scheduler.cpp565 if (def.isFixed() && def.physReg() == exec)
H A Daco_instruction_selection.cpp139 assert(mask.isUndefined() || mask.isTemp() || (mask.isFixed() && mask.physReg() == exec));
156 } else if (mask.physReg() == exec) {

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