Searched refs:shader_count (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_interface.h44 void aco_compile_shader(unsigned shader_count, struct nir_shader* const* shaders,
H A Daco_instruction_selection.h117 isel_context setup_isel_context(Program* program, unsigned shader_count,
H A Daco_interface.cpp77 aco_compile_shader(unsigned shader_count, struct nir_shader* const* shaders, argument
98 aco::select_program(program.get(), shader_count, shaders, &config, args);
238 legacy_binary->base.stage = shaders[shader_count - 1]->info.stage;
H A Daco_instruction_selection_setup.cpp821 setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* const* shaders, argument
825 for (unsigned i = 0; i < shader_count; i++) {
899 assert(shader_count == 1);
902 for (unsigned i = 0; i < shader_count; i++) {
907 for (unsigned i = 0; i < shader_count; i++)
H A Daco_ir.h2145 void select_program(Program* program, unsigned shader_count, struct nir_shader* const* shaders,
H A Daco_instruction_selection.cpp11548 select_program(Program* program, unsigned shader_count, struct nir_shader* const* shaders, argument
11551 isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
11555 for (unsigned i = 0; i < shader_count; i++) {
11586 ctx.tcs_in_out_eq ? i == 0 : (shader_count >= 2 && !empty_shader && !(ngg_gs && i == 1));
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Dir3_compiler.h38 uint32_t shader_count; member in struct:ir3_compiler
H A Dir3_shader.c275 shader->id = ++shader->compiler->shader_count;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler.h53 uint32_t shader_count; member in struct:etna_compiler
H A Detnaviv_shader.c467 shader->id = p_atomic_inc_return(&compiler->shader_count);
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_compiler.h44 uint32_t shader_count; member in struct:ir3_compiler
H A Dir3_shader.c592 shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_shader.c596 int shader_count,
638 assert(shader_count == 1);
644 &variant->info, shaders, shader_count,
682 int shader_count,
697 return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
593 shader_variant_create(struct radv_device * device,struct radv_shader_module * module,struct nir_shader * const * shaders,int shader_count,gl_shader_stage stage,struct radv_nir_compiler_options * options,bool gs_copy_shader,void ** code_out,unsigned * code_size_out) argument
679 radv_shader_variant_create(struct radv_device * device,struct radv_shader_module * module,struct nir_shader * const * shaders,int shader_count,struct radv_pipeline_layout * layout,const struct radv_shader_variant_key * key,void ** code_out,unsigned * code_size_out) argument
H A Dradv_shader.h364 int shader_count,
H A Dradv_nir_to_llvm.c3660 int shader_count,
3683 for(int i = 0; i < shader_count; ++i)
3692 for (int i = 0; i < shader_count; ++i) {
3699 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
3700 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
3718 if (shader_count >= 2)
3723 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3726 for(int i = 0; i < shader_count;
3658 ac_translate_nir_to_llvm(struct ac_llvm_compiler * ac_llvm,struct nir_shader * const * shaders,int shader_count,struct radv_shader_variant_info * shader_info,const struct radv_nir_compiler_options * options) argument
[all...]
H A Dradv_pipeline.c1760 int shader_count = 0; local in function:radv_link_shaders
1763 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1766 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1769 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1772 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1775 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1778 if (shader_count > 1) {
1779 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
1786 for (int i = 0; i < shader_count; ++i) {
1800 for (int i = 1; i < shader_count;
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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_shader.c1715 radv_dump_nir_shaders(struct nir_shader *const *shaders, int shader_count) argument
1723 for (int i = 0; i < shader_count; ++i)
1739 struct nir_shader *const *shaders, int shader_count, gl_shader_stage stage,
1791 &args, gs_copy_shader ? MESA_SHADER_VERTEX : shaders[shader_count - 1]->info.stage,
1792 shader_count >= 2,
1793 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
1800 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1805 aco_compile_shader(shader_count, shaders, &binary, &args);
1819 for (int i = 1; i < shader_count;
1738 shader_variant_compile(struct radv_device * device,struct vk_shader_module * module,struct nir_shader * const * shaders,int shader_count,gl_shader_stage stage,struct radv_shader_info * info,struct radv_nir_compiler_options * options,bool gs_copy_shader,bool trap_handler_shader,bool keep_shader_info,bool keep_statistic_info,struct radv_shader_binary ** binary_out) argument
1852 radv_shader_variant_compile(struct radv_device * device,struct vk_shader_module * module,struct nir_shader * const * shaders,int shader_count,struct radv_pipeline_layout * layout,const struct radv_pipeline_key * key,struct radv_shader_info * info,bool keep_shader_info,bool keep_statistic_info,struct radv_shader_binary ** binary_out) argument
[all...]
H A Dradv_nir_to_llvm.c2388 int shader_count, const struct radv_shader_args *args)
2412 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
2428 if (shader_count >= 2 || is_ngg)
2439 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
2454 if (ctx.ac.chip_class == GFX10 && shader_count == 1)
2458 for (int shader_idx = 0; shader_idx < shader_count; ++shader_idx) {
2540 if (shader_count >= 2 || is_ngg) {
2557 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
2561 if (shader_count >
2387 ac_translate_nir_to_llvm(struct ac_llvm_compiler * ac_llvm,struct nir_shader * const * shaders,int shader_count,const struct radv_shader_args * args) argument
2814 llvm_compile_shader(struct radv_device * device,unsigned shader_count,struct nir_shader * const * shaders,struct radv_shader_binary ** binary,struct radv_shader_args * args) argument
[all...]
H A Dradv_shader.h513 int shader_count, struct radv_pipeline_layout *layout, const struct radv_pipeline_key *key,
H A Dradv_pipeline.c2305 int shader_count = 0; local in function:radv_link_shaders
2308 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2311 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2314 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2317 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2320 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2323 ordered_shaders[shader_count++] = shaders[MESA_SHADER_COMPUTE];
2330 if (!optimize_conservatively && shader_count > 1) {
2331 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2338 for (int i = 1; i < shader_count;
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H A Dradv_private.h2625 void llvm_compile_shader(struct radv_device *device, unsigned shader_count,
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.2.0.rst1114 - etnaviv: move shader_count to etna_compiler

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