Searched refs:tile_mode (Results 1 - 25 of 128) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/freedreno/fdl/
H A Dfd6_format_table.h43 enum a6xx_tile_mode tile_mode) ATTRIBUTE_CONST;
45 enum a6xx_tile_mode tile_mode) ATTRIBUTE_CONST;
47 enum a6xx_tile_mode tile_mode) ATTRIBUTE_CONST;
49 enum a6xx_tile_mode tile_mode) ATTRIBUTE_CONST;
H A Dfd_layout_test.h32 uint32_t tile_mode : 2; member in struct:testcase::__anonbd1a3f260108
H A Dfd5_layout_test.c42 .tile_mode = TILE5_3,
65 .tile_mode = TILE5_3,
86 .tile_mode = TILE5_3,
H A Dfd5_layout.c58 if (layout->cpp < 4 && layout->tile_mode)
65 uint32_t tile_mode = fdl_tile_mode(layout, level); local in function:fdl5_layout
70 if (tile_mode) {
H A Dfd6_layout_test.c61 .tile_mode = TILE6_3,
404 .tile_mode = TILE6_3,
428 .tile_mode = TILE6_3,
451 .tile_mode = TILE6_3,
492 .tile_mode = TILE6_3,
532 .tile_mode = TILE6_3,
578 .tile_mode = TILE6_3,
624 .tile_mode = TILE6_3,
671 .tile_mode = TILE6_3,
H A Dfreedreno_layout.h109 * general you should not directly look at fdl_layout::tile_mode,
110 * but instead use fdl_surface::tile_mode which will correctly take
113 uint32_t tile_mode : 2; member in struct:fdl_layout
219 if (layout->tile_mode && fdl_level_linear(layout, level))
222 return layout->tile_mode;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_format.h39 void fd6_tex_swiz(enum pipe_format format, enum a6xx_tile_mode tile_mode, unsigned char *swiz,
H A Dfd6_format.c55 fd6_tex_swiz(enum pipe_format format, enum a6xx_tile_mode tile_mode, unsigned char *swiz, unsigned swizzle_r, argument
94 fd6_tex_swiz(format, rsc->layout.tile_mode, swiz, swizzle_r, swizzle_g, swizzle_b, swizzle_a);
96 return A6XX_TEX_CONST_0_FMT(fd6_texture_format(format, rsc->layout.tile_mode)) |
98 A6XX_TEX_CONST_0_SWAP(fd6_texture_swap(format, rsc->layout.tile_mode)) |
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_transfer.h18 uint16_t tile_mode; member in struct:nv50_m2mf_rect
H A Dnv50_miptree.c35 uint32_t tile_mode = 0x000; local in function:nv50_tex_choose_tile_dims_helper
37 if (ny > 64) tile_mode = 0x040; /* height 128 tiles */
39 if (ny > 32) tile_mode = 0x030; /* height 64 tiles */
41 if (ny > 16) tile_mode = 0x020; /* height 32 tiles */
43 if (ny > 8) tile_mode = 0x010; /* height 16 tiles */
46 return tile_mode;
48 if (tile_mode > 0x020)
49 tile_mode = 0x020;
51 if (nz > 16 && tile_mode < 0x020)
52 return tile_mode |
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_transfer.h18 uint16_t tile_mode; member in struct:nv50_m2mf_rect
H A Dnv50_miptree.c35 uint32_t tile_mode = 0x000; local in function:nv50_tex_choose_tile_dims_helper
37 if (ny > 64) tile_mode = 0x040; /* height 128 tiles */
39 if (ny > 32) tile_mode = 0x030; /* height 64 tiles */
41 if (ny > 16) tile_mode = 0x020; /* height 32 tiles */
43 if (ny > 8) tile_mode = 0x010; /* height 16 tiles */
46 return tile_mode;
48 if (tile_mode > 0x020)
49 tile_mode = 0x020;
51 if (nz > 16 && tile_mode < 0x020)
52 return tile_mode |
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/xsrc/external/mit/libdrm/dist/nouveau/
H A Dabi16.c294 bo->config.nvc0.tile_mode = info->tile_mode;
299 bo->config.nv50.tile_mode = info->tile_mode << 4;
302 bo->config.nv04.surf_pitch = info->tile_mode;
339 info->tile_mode = config->nvc0.tile_mode;
344 info->tile_mode = config->nv50.tile_mode >> 4;
347 info->tile_mode
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/xsrc/external/mit/libdrm/dist/radeon/
H A Dradeon_surface.c1288 unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
1353 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D;
1356 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_2AA;
1359 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_4AA;
1362 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_8AA;
1370 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1373 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1381 *tile_mode = SI_TILE_MODE_COLOR_2D_8BPP;
1384 *tile_mode = SI_TILE_MODE_COLOR_2D_16BPP;
1387 *tile_mode
1286 si_surface_sanity(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,unsigned mode,unsigned * tile_mode,unsigned * stencil_tile_mode) argument
1517 si_surface_init_linear_aligned(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,unsigned tile_mode,uint64_t offset,unsigned start_level) argument
1550 si_surface_init_1d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,uint64_t offset,unsigned start_level) argument
1599 si_surface_init_1d_miptrees(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,unsigned tile_mode,unsigned stencil_tile_mode) argument
1617 si_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned num_pipes,unsigned num_banks,unsigned tile_split,uint64_t offset,unsigned start_level) argument
1701 si_surface_init_2d_miptrees(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,unsigned tile_mode,unsigned stencil_tile_mode) argument
1728 unsigned mode, tile_mode, stencil_tile_mode; local in function:si_surface_init
1788 unsigned mode, tile_mode, stencil_tile_mode; local in function:si_surface_best
1857 cik_get_2d_params(struct radeon_surface_manager * surf_man,unsigned bpe,unsigned nsamples,bool is_color,unsigned tile_mode,uint32_t * num_pipes,uint32_t * tile_split_ptr,uint32_t * num_banks,uint32_t * macro_tile_aspect,uint32_t * bank_w,uint32_t * bank_h) argument
2116 cik_surface_sanity(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,unsigned mode,unsigned * tile_mode,unsigned * stencil_tile_mode) argument
2215 cik_surface_init_2d(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,struct radeon_surface_level * level,unsigned bpe,unsigned tile_mode,unsigned tile_split,unsigned num_pipes,unsigned num_banks,uint64_t offset,unsigned start_level) argument
2304 cik_surface_init_2d_miptrees(struct radeon_surface_manager * surf_man,struct radeon_surface * surf,unsigned tile_mode,unsigned stencil_tile_mode) argument
2333 unsigned mode, tile_mode, stencil_tile_mode; local in function:cik_surface_init
2393 unsigned mode, tile_mode, stencil_tile_mode; local in function:cik_surface_best
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_miptree.c180 mt->level[0].tile_mode = 0x10;
217 lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
219 tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
220 tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode);
221 tsz = NVC0_TILE_SIZE_Z(lvl->tile_mode);
234 NVC0_TILE_SIZE(mt->level[0].tile_mode));
253 switch (NVC0_TILE_MODE_Y(config->nvc0.tile_mode)) {
377 bo_config.nvc0.tile_mode = mt->level[0].tile_mode;
410 unsigned tds = NVC0_TILE_SHIFT_Z(mt->level[l].tile_mode);
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a3xx/
H A Dfd3_resource.c36 if (rsc->layout.tile_mode && prsc->target != PIPE_TEXTURE_CUBE)
46 if (rsc->layout.tile_mode) {
/xsrc/external/mit/xf86-video-nouveau/dist/src/
H A Dnvc0_accel.h125 (bo->config.nvc0.tile_mode << 18) |
133 unsigned tile_mode = bo->config.nvc0.tile_mode; local in function:PUSH_TIC
140 ((tile_mode & 0x007)) |
141 ((tile_mode & 0x070) >> (4 - 3)) |
142 ((tile_mode & 0x700) >> (8 - 6)));
H A Dnouveau_copy85b5.c59 PUSH_DATA (push, src->config.nv50.tile_mode);
67 PUSH_DATA (push, dst->config.nv50.tile_mode);
H A Dnouveau_copy90b5.c59 PUSH_DATA (push, src->config.nvc0.tile_mode);
67 PUSH_DATA (push, dst->config.nvc0.tile_mode);
H A Dnouveau_copya0b5.c59 PUSH_DATA (push, 0x00001000 | src->config.nvc0.tile_mode);
66 PUSH_DATA (push, 0x000001000 | dst->config.nvc0.tile_mode);
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_formats.c81 tu6_format_color_unchecked(VkFormat vk_format, enum a6xx_tile_mode tile_mode) argument
85 .fmt = fd6_color_format(format, tile_mode),
86 .swap = fd6_color_swap(format, tile_mode),
109 tu6_format_color(VkFormat vk_format, enum a6xx_tile_mode tile_mode) argument
111 struct tu_native_format fmt = tu6_format_color_unchecked(vk_format, tile_mode);
117 tu6_format_texture_unchecked(VkFormat vk_format, enum a6xx_tile_mode tile_mode) argument
121 .fmt = fd6_texture_format(format, tile_mode),
122 .swap = fd6_texture_swap(format, tile_mode),
151 tu6_format_texture(VkFormat vk_format, enum a6xx_tile_mode tile_mode) argument
153 struct tu_native_format fmt = tu6_format_texture_unchecked(vk_format, tile_mode);
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H A Dtu_image.c251 struct tu_native_format fmt = tu6_format_texture(format, layout->tile_mode);
256 fmt.tile_mode = fdl_tile_mode(layout, range->baseMipLevel);
276 A6XX_TEX_CONST_0_TILE_MODE(fmt.tile_mode) |
357 .tile_mode = fmt.tile_mode,
386 struct tu_native_format cfmt = tu6_format_color(format, layout->tile_mode);
387 cfmt.tile_mode = fmt.tile_mode;
396 A6XX_IBO_0_TILE_MODE(fmt.tile_mode);
420 (fmt.tile_mode
581 enum a6xx_tile_mode tile_mode = TILE6_3; local in function:tu_CreateImage
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_miptree.c241 mt->level[0].tile_mode = 0x10;
283 * into tile_mode's y field. Other tile dimensions are always 1
288 lvl->tile_mode = ((uint32_t)modifier & 0xf) << 4;
290 lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
292 tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */
293 tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode);
294 tsz = NVC0_TILE_SIZE_Z(lvl->tile_mode);
307 NVC0_TILE_SIZE(mt->level[0].tile_mode));
329 if (NVC0_TILE_MODE_Y(config->nvc0.tile_mode) > 5)
339 NVC0_TILE_MODE_Y(config->nvc0.tile_mode));
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_dma.c106 unsigned tile_mode = info->si_tile_mode_array[index]; local in function:si_dma_copy_tile
129 array_mode = G_009910_ARRAY_MODE(tile_mode);
142 bank_h = G_009910_BANK_HEIGHT(tile_mode);
143 bank_w = G_009910_BANK_WIDTH(tile_mode);
144 mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
147 nbanks = G_009910_NUM_BANKS(tile_mode);
151 pipe_config = G_009910_PIPE_CONFIG(tile_mode);
152 mt = G_009910_MICRO_TILE_MODE(tile_mode);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/
H A Dfreedreno_resource.h105 unsigned tile_mode : 2; member in struct:fd_resource
200 return rsc->ubwc_size && rsc->tile_mode &&

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