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      1 /*	$NetBSD: pci_machdep.c,v 1.20 2014/03/29 19:28:30 christos Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1999, 2000 Matthew R. Green
      5  * Copyright (c) 2001 Valeriy E. Ushakov
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. The name of the author may not be used to endorse or promote products
     17  *    derived from this software without specific prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     24  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     26  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     27  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Machine-dependent PCI bits for PCI controller in microSPARC-IIep.
     34  * References are to the microSPARC-IIep manual unless noted otherwise.
     35  */
     36 
     37 #include <sys/cdefs.h>
     38 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.20 2014/03/29 19:28:30 christos Exp $");
     39 
     40 #if defined(DEBUG) && !defined(SPARC_PCI_DEBUG)
     41 #define SPARC_PCI_DEBUG
     42 #endif
     43 
     44 #ifdef SPARC_PCI_DEBUG
     45 #define SPDB_CONF	0x01
     46 #define SPDB_INTR	0x04
     47 #define SPDB_INTMAP	0x08
     48 #define SPDB_INTFIX	0x10
     49 #define SPDB_PROBE	0x20
     50 int sparc_pci_debug = 0;
     51 #define DPRINTF(l, s)	do { 			\
     52 	if (sparc_pci_debug & (l))		\
     53 		printf s;			\
     54 } while (/* CONSTCOND */ 0)
     55 #else
     56 #define DPRINTF(l, s)
     57 #endif
     58 
     59 #include <sys/types.h>
     60 #include <sys/param.h>
     61 #include <sys/time.h>
     62 #include <sys/systm.h>
     63 #include <sys/errno.h>
     64 #include <sys/device.h>
     65 #include <sys/malloc.h>
     66 
     67 #include <sys/bus.h>
     68 #include <machine/autoconf.h>
     69 
     70 #include <machine/ctlreg.h>
     71 #include <sparc/sparc/asm.h>
     72 
     73 #include <dev/pci/pcivar.h>
     74 #include <dev/pci/pcireg.h>
     75 
     76 #include <dev/ofw/ofw_pci.h>
     77 
     78 #include <sparc/sparc/msiiepreg.h>
     79 #include <sparc/sparc/msiiepvar.h>
     80 
     81 /*
     82  * Table 9-1 (p. 129).
     83  *   Configuration space access.  This goes via MMU bypass ASI.
     84  */
     85 #define PCI_MODE1_ADDRESS_REG_PA	0x30080000
     86 #define	PCI_MODE1_DATA_REG_PA		0x300a0000
     87 
     88 /*
     89  * Footnote 1 in Table 9-1 (p. 129):
     90  *
     91  *   Three least significant bits of the configuration data space
     92  *   access must match those of the configuration address space access.
     93  */
     94 #define PCI_MODE1_DATA_REG_MASK	0x7
     95 
     96 
     97 /*
     98  * PROMs in ms-IIep systems just lie about PCI and EBus interrupts, so
     99  * we just hardcode the wiring based on the model we are running on.
    100  * Probably we can do some forth hacking in boot loader's prompatch
    101  * (that's what it was introduced for), but for now it's way more
    102  * simple to just hardcode it here.
    103  * XXX: Unknown mappings for PCI slots set to line 8.
    104  */
    105 
    106 struct mspcic_pci_intr_wiring {
    107 	u_int		mpiw_bus;
    108 	u_int		mpiw_device;
    109 	u_int		mpiw_function;
    110 	pci_intr_line_t	mpiw_line[4];	/* Int A (0) - Int D (3) */
    111 };
    112 
    113 static struct mspcic_pci_intr_wiring krups_pci_intr_wiring[] = {
    114 	{ 0, 0, 1,    { 1, 0, 0, 0 } },	/* ethernet */
    115 	{ 0, 1, 0,    { 2, 0, 0, 0 } },	/* vga */
    116 };
    117 
    118 static struct mspcic_pci_intr_wiring espresso_pci_intr_wiring[] = {
    119 	{ 0,  0, 1,    { 1, 0, 0, 0 } },	/* ethernet */
    120 	{ 0,  1, 0,    { 2, 0, 0, 0 } },	/* vga */
    121 	{ 0,  2, 0,    { 6, 7, 8, 8 } },	/* pci slot1 */
    122 	{ 0,  2, 1,    { 6, 7, 8, 8 } },	/* pci slot1 */
    123 	{ 0,  2, 2,    { 6, 7, 8, 8 } },	/* pci slot1 */
    124 	{ 0,  2, 3,    { 6, 7, 8, 8 } },	/* pci slot1 */
    125 	{ 0,  2, 4,    { 6, 7, 8, 8 } },	/* pci slot1 */
    126 	{ 0,  2, 5,    { 6, 7, 8, 8 } },	/* pci slot1 */
    127 	{ 0,  2, 6,    { 6, 7, 8, 8 } },	/* pci slot1 */
    128 	{ 0,  2, 7,    { 6, 7, 8, 8 } },	/* pci slot1 */
    129 	{ 0,  3, 0,    { 7, 8, 8, 8 } },	/* pci slot2 */
    130 	{ 0,  3, 1,    { 7, 8, 8, 8 } },	/* pci slot2 */
    131 	{ 0,  3, 2,    { 7, 8, 8, 8 } },	/* pci slot2 */
    132 	{ 0,  3, 3,    { 7, 8, 8, 8 } },	/* pci slot2 */
    133 	{ 0,  3, 4,    { 7, 8, 8, 8 } },	/* pci slot2 */
    134 	{ 0,  3, 5,    { 7, 8, 8, 8 } },	/* pci slot2 */
    135 	{ 0,  3, 6,    { 7, 8, 8, 8 } },	/* pci slot2 */
    136 	{ 0,  3, 7,    { 7, 8, 8, 8 } },	/* pci slot2 */
    137 	{ 0,  7, 0,    { 4, 0, 0, 0 } },	/* isa */
    138 	{ 0, 16, 0,    { 5, 0, 0, 0 } },	/* eide */
    139 	{ 0, 20, 0,    { 5, 0, 0, 0 } },	/* usb */
    140 };
    141 
    142 struct mspcic_known_model {
    143 	const char *model;
    144 	struct mspcic_pci_intr_wiring *map;
    145 	int mapsize;
    146 };
    147 
    148 #define MSPCIC_MODEL_WIRING(name,map) \
    149 	{ name, map, sizeof(map)/sizeof(map[0]) }
    150 
    151 static struct mspcic_known_model mspcic_known_models[] = {
    152 	MSPCIC_MODEL_WIRING("SUNW,501-4267", krups_pci_intr_wiring),
    153 	MSPCIC_MODEL_WIRING("SUNW,375-0059", espresso_pci_intr_wiring),
    154 	{ NULL, NULL, 0}
    155 };
    156 
    157 
    158 static struct mspcic_pci_intr_wiring *wiring_map;
    159 static int wiring_map_size;
    160 
    161 
    162 void
    163 pci_attach_hook(device_t parent, device_t self,
    164 		struct pcibus_attach_args *pba)
    165 {
    166 	struct mspcic_known_model *p;
    167 	char buf[32];
    168 	char *model;
    169 
    170 	/* We only need to run once (root PCI bus is 0) */
    171 	if (pba->pba_bus != 0)
    172 		return;
    173 
    174 	model = prom_getpropstringA(prom_findroot(), "model",
    175 				    buf, sizeof(buf));
    176 	if (model == NULL)
    177 		panic("pci_attach_hook: no \"model\" property");
    178 
    179 	printf(": model %s", model);
    180 
    181 	for (p = mspcic_known_models; p->model != NULL; ++p)
    182 		if (strcmp(model, p->model) == 0) {
    183 			printf(": interrupt wiring known");
    184 			wiring_map = p->map;
    185 			wiring_map_size = p->mapsize;
    186 			return;
    187 		}
    188 
    189 	/* not found */
    190 	printf(": don't know how interrupts are wired\n");
    191 	panic("pci_attach_hook: unknown model %s", model);
    192 }
    193 
    194 
    195 int
    196 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
    197 {
    198 
    199 	return 32;
    200 }
    201 
    202 
    203 pcitag_t
    204 pci_make_tag(pci_chipset_tag_t pc, int b, int d, int f)
    205 {
    206 	struct mspcic_softc *sc = (struct mspcic_softc *)pc->cookie;
    207 	pcitag_t tag;
    208 	int node, len;
    209 #ifdef SPARC_PCI_DEBUG
    210 	char name[80];
    211 
    212 	memset(name, 0, sizeof(name));
    213 #endif
    214 	tag = PCITAG_CREATE(-1, b, d, f);
    215 	if (b >= 256 || d >= 32 || f >= 8) {
    216 		printf("pci_make_tag: bad request %d/%d/%d\n", b, d, f);
    217 		return tag;	/* a dead one */
    218 	}
    219 
    220 	/*
    221 	 * XXX: OFW 3.11 doesn't have "bus-range" property on its
    222 	 * "/pci" node.  As a workaround we start with the first child
    223 	 * of "/pci" instead of matching the bus number against the
    224 	 * "bus-range" of the "/pci" node.
    225 	 *
    226 	 * Traverse all peers until we find the node.
    227 	 */
    228 	for (node = OF_child(sc->sc_node); node != 0; node = OF_peer(node)) {
    229 		struct ofw_pci_register reg;
    230 		uint32_t busrange[2];
    231 		int class;
    232 		pcireg_t busdata;
    233 		pcitag_t bustag;
    234 
    235 #ifdef SPARC_PCI_DEBUG
    236 		if (sparc_pci_debug & SPDB_PROBE) {
    237 			OF_getprop(node, "name", &name, sizeof(name));
    238 			printf("> checking node %x %s\n", node, name);
    239 		}
    240 #endif
    241 		/*
    242 		 * Check for PCI-PCI bridges.  If the device we want is
    243 		 * in the bus-range for that bridge, work our way down.
    244 		 */
    245 		while ((OF_getprop(node, "bus-range", (void *)&busrange,
    246 				   sizeof(busrange)) == sizeof(busrange))
    247 		       && (b >= busrange[0] && b <= busrange[1]))
    248 		{
    249 			/* go down one level */
    250 			node = OF_child(node);
    251 #ifdef SPARC_PCI_DEBUG
    252 			if (sparc_pci_debug & SPDB_PROBE) {
    253 				OF_getprop(node, "name", &name, sizeof(name));
    254 				printf("> going down to node %x %s\n",
    255 					node, name);
    256 			}
    257 #endif
    258 		}
    259 
    260 		/*
    261 		 * We only really need the first `reg' property.
    262 		 *
    263 		 * For simplicity, we'll query the `reg' when we
    264 		 * need it.  Otherwise we could malloc() it, but
    265 		 * that gets more complicated.
    266 		 */
    267 		len = OF_getproplen(node, "reg");
    268 		OF_getprop(node, "reg", (void *)&reg, sizeof(reg));
    269 
    270 		/*
    271 		 * Check for (OFW unconfigured) bridges that we fixed up.
    272 		 * We'll set this top-level bridge's node in the tag,
    273 		 * so that we can use it later for interrupt wiring.
    274 		 */
    275 		if (b > 0) {
    276 			len = OF_getproplen(node, "class-code");
    277 			if (!len)
    278 				continue;
    279 			OF_getprop(node, "class-code", &class, len);
    280 			if (IS_PCI_BRIDGE(class)) {
    281 				bustag = PCITAG_CREATE(node,
    282 				    OFW_PCI_PHYS_HI_BUS(reg.phys_hi),
    283 				    OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi),
    284 				    OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi));
    285 				busdata = pci_conf_read(NULL, bustag,
    286 				    PCI_BRIDGE_BUS_REG);
    287 				if (b != ((busdata >> 8) & 0xff))
    288 					continue;
    289 
    290 #ifdef SPARC_PCI_DEBUG
    291 				if (sparc_pci_debug & SPDB_PROBE) {
    292 					OF_getprop(node, "name", &name,
    293 					    sizeof(name));
    294 					printf("> matched device behind node "
    295 					    "%x %s (bus %d)\n", node, name, b);
    296 				}
    297 #endif
    298 			} else
    299 				continue;
    300 		} else {
    301 			if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
    302 				continue;
    303 			if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
    304 				continue;
    305 			if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
    306 				continue;
    307 		}
    308 
    309 		/* Got a match */
    310 		tag = PCITAG_CREATE(node, b, d, f);
    311 		DPRINTF(SPDB_PROBE, ("> found node %x %s\n", node, name));
    312 		return tag;
    313 	}
    314 
    315 	/* No device found - return a dead tag */
    316 	return tag;
    317 }
    318 
    319 
    320 void
    321 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
    322 		  int *bp, int *dp, int *fp)
    323 {
    324 
    325 	if (bp != NULL)
    326 		*bp = PCITAG_BUS(tag);
    327 	if (dp != NULL)
    328 		*dp = PCITAG_DEV(tag);
    329 	if (fp != NULL)
    330 		*fp = PCITAG_FUN(tag);
    331 }
    332 
    333 
    334 pcireg_t
    335 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
    336 {
    337 	uint32_t mode1_addr;
    338 	uint32_t mode1_data_reg_pa;
    339 	uint32_t val;
    340 
    341 	DPRINTF(SPDB_CONF,
    342 		("pci_conf_read:  tag=%x.%x (%d/%d/%d), reg=%02x; ",
    343 		 PCITAG_NODE(tag), PCITAG_OFFSET(tag),
    344 		 PCITAG_BUS(tag), PCITAG_DEV(tag), PCITAG_FUN(tag),
    345 		 reg));
    346 
    347 #ifdef DIAGNOSTIC
    348 	if (reg & 0x3)
    349 		panic("pci_conf_read: reg %x unaligned", reg);
    350 #endif
    351 
    352 	if (PCITAG_NODE(tag) == -1) {
    353 		DPRINTF(SPDB_CONF, ("\n"));
    354 		return ~0;
    355 	}
    356 
    357 	if ((unsigned int)reg >= PCI_CONF_SIZE)
    358 		return ~0;
    359 
    360 	mode1_addr = PCITAG_OFFSET(tag) | reg;
    361 	mode1_data_reg_pa = PCI_MODE1_DATA_REG_PA
    362 		| (reg & PCI_MODE1_DATA_REG_MASK);
    363 
    364 	sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, htole32(mode1_addr));
    365 	val = le32toh(lda(mode1_data_reg_pa, ASI_BYPASS));
    366 
    367 	DPRINTF(SPDB_CONF, ("reading %08x\n", val));
    368 
    369 	return val;
    370 }
    371 
    372 
    373 void
    374 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
    375 {
    376 	uint32_t mode1_addr;
    377 	uint32_t mode1_data_reg_pa;
    378 
    379 	DPRINTF(SPDB_CONF,
    380 		("pci_conf_write: tag=%x.%x (%d/%d/%d); reg=%02x; ",
    381 		 PCITAG_NODE(tag), PCITAG_OFFSET(tag),
    382 		 PCITAG_BUS(tag), PCITAG_DEV(tag), PCITAG_FUN(tag),
    383 		 reg));
    384 
    385 #ifdef DIAGNOSTIC
    386 	if (reg & 0x3)
    387 		panic("pci_conf_write: reg %x unaligned", reg);
    388 #endif
    389 
    390 	if (PCITAG_NODE(tag) == -1) {
    391 		DPRINTF(SPDB_CONF, ("\n"));
    392 		return;
    393 	}
    394 
    395 	if ((unsigned int)reg >= PCI_CONF_SIZE)
    396 		return;
    397 
    398 	mode1_addr = PCITAG_OFFSET(tag) | reg;
    399 	mode1_data_reg_pa = PCI_MODE1_DATA_REG_PA
    400 		| (reg & PCI_MODE1_DATA_REG_MASK);
    401 
    402 	DPRINTF(SPDB_CONF, ("writing %08x\n", data));
    403 
    404 	sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, htole32(mode1_addr));
    405 	sta(mode1_data_reg_pa, ASI_BYPASS, htole32(data));
    406 }
    407 
    408 
    409 /* ======================================================================
    410  *
    411  *	       PCI bus interrupt manipulation functions
    412  */
    413 
    414 int
    415 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
    416 {
    417 	int i, node;
    418 	pcitag_t tag;
    419 	pcireg_t val;
    420 	pci_intr_pin_t pin;
    421 
    422 	DPRINTF(SPDB_INTMAP,
    423 		("pci_intr_map(%d/%d/%d) -> ",
    424 		 pa->pa_bus, pa->pa_device, pa->pa_function));
    425 
    426 	tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device,
    427 	    pa->pa_function);
    428 	node = PCITAG_NODE(tag);
    429 	val = pci_conf_read(NULL, tag, PCI_INTERRUPT_REG);
    430 	pin = PCI_INTERRUPT_PIN(val);
    431 
    432 	/*
    433 	 * Pin should be A(1) to D(4) - use values 0 to 3 respectively to
    434 	 * represent them.  Built-in devices might show pin 0, so assume
    435 	 * pin A for those - the static wiring map has the correct line.
    436 	 */
    437 	if (pin)
    438 		pin -= 1;
    439 
    440 	for (i = 0; i < wiring_map_size; ++i) {
    441 		struct mspcic_pci_intr_wiring *w = &wiring_map[i];
    442 
    443 		/* Device on PCI bus 0 */
    444 		if (pa->pa_bus == w->mpiw_bus
    445 		    && pa->pa_device == w->mpiw_device
    446 		    && pa->pa_function == w->mpiw_function)
    447 		{
    448 			if (w->mpiw_line[pin] > 7) {
    449 				DPRINTF(SPDB_INTMAP, ("not mapped\n"));
    450 				return -1;
    451 			}
    452 			DPRINTF(SPDB_INTMAP, ("pin %c line %d\n", 'A' + pin,
    453 			    w->mpiw_line[pin]));
    454 			*ihp = w->mpiw_line[pin];
    455 			return 0;
    456 		/* Device on other PCI bus - find top-level bridge device */
    457 		} else if (pa->pa_bus) {
    458 			struct ofw_pci_register reg;
    459 
    460 			OF_getprop(node, "reg", (void *)&reg, sizeof(reg));
    461 			if (OFW_PCI_PHYS_HI_BUS(reg.phys_hi) == w->mpiw_bus
    462 			    && OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)
    463 			    == w->mpiw_device
    464 			    && OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)
    465 			    == w->mpiw_function) {
    466 				int j;
    467 
    468 				/* PCI bridge interrupt swizzle */
    469 				for (j = 0; j < PCI_INTERRUPT_LINE(val); j++)
    470 					pin = (pin + (pa->pa_device % 4)) % 4;
    471 
    472 				if (w->mpiw_line[pin] > 7) {
    473 					DPRINTF(SPDB_INTMAP, ("pin %c "
    474 					    "not mapped\n", pin));
    475 					return -1;
    476 				}
    477 				DPRINTF(SPDB_INTMAP, ("pin %c line %d "
    478 				    "via bridge (%d/%d/%d) depth %d\n",
    479 				    'A' + pin, w->mpiw_line[pin],
    480 				    w->mpiw_bus, w->mpiw_device,
    481 				    w->mpiw_function,
    482 				    PCI_INTERRUPT_LINE(val)));
    483 				*ihp = w->mpiw_line[pin];
    484 				return 0;
    485 			}
    486 		}
    487 	}
    488 
    489 	DPRINTF(SPDB_INTMAP, ("not found\n"));
    490 	return -1;
    491 }
    492 
    493 
    494 const char *
    495 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf,
    496     size_t len)
    497 {
    498 	int pil;
    499 
    500 	pil = mspcic_assigned_interrupt(ih);
    501 	snprintf(buf, len, "line %d (pil %d)", ih, pil);
    502 	return buf;
    503 }
    504 
    505 
    506 const struct evcnt *
    507 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
    508 {
    509 
    510 	/* XXX for now, no evcnt parent reported */
    511 	return NULL;
    512 }
    513 
    514 int
    515 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
    516 		 int attr, uint64_t data)
    517 {
    518 
    519 	switch (attr) {
    520 	case PCI_INTR_MPSAFE:
    521 		return 0;
    522 	default:
    523 		return ENODEV;
    524 	}
    525 }
    526 
    527 void *
    528 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih,
    529 		   int level, int (*func)(void *), void *arg)
    530 {
    531 	struct mspcic_softc *sc = (struct mspcic_softc *)pc->cookie;
    532 	void *cookie;
    533 
    534 	DPRINTF(SPDB_INTR,
    535 		("pci_intr_establish(line %d, ipl %d)\n", ih, level));
    536 
    537 	cookie = bus_intr_establish(sc->sc_memt, ih, level, func, arg);
    538 
    539 	/*
    540 	 * TODO: to implement pci_intr_disestablish we need to capture
    541 	 * the 'intrhand' returned by bus_intr_establish above and the
    542 	 * pil the handler was established for, but we don't need to
    543 	 * disestablish pci interrupts for now (and I doubt we will),
    544 	 * so why bother.
    545 	 */
    546 
    547 	DPRINTF(SPDB_INTR,
    548 		("pci_intr_establish: returning handle %p\n", cookie));
    549 	return cookie;
    550 }
    551 
    552 
    553 void
    554 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
    555 {
    556 
    557 	DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
    558 	panic("pci_intr_disestablish: not implemented");
    559 }
    560