Coyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi>
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.Dd August 15, 2010 .Dt ACPICPU 4 .Os .Sh NAME .Nm acpicpu .Nd ACPI CPU .Sh SYNOPSIS .Cd "acpicpu* at acpi?" .Sh DESCRIPTION The .Nm device driver supports certain processor features that are either only available via .Tn ACPI or that require .Tn ACPI to function properly. Typically the .Tn ACPI processor functionality is grouped into so-called C-, P-, and T-states. .Ss C-states The processor power states, or C-states, are low-power modes that can be used when the .Tn CPU is idle. The idea is not new: already in the .Tn 80486 processor a specific instruction
q Tn HLT was used for this purpose. This was later accompanied by a pair of other instructions
q Tn MONITOR , MWAIT . By default, .Nx may use either one; see the c machdep.idle-mechanism .Xr sysctl 8 variable. .Tn ACPI provides the latest amendment.
p The following C-states are typically available. Additional processor or vendor specific states (C4, ..., Cn) are handled internally by .Nm .
p l -tag -width C1 -offset indent t Dv C0 This is the normal state of a processor; the .Tn CPU is busy executing instructions. t Dv C1 This is the state that is typically reached via the mentioned .Tn x86 instructions. On a typical processor, .Dv C1 turns off the main internal .Tn CPU clock, leaving .Tn APIC running at full speed. The .Tn CPU is free to temporarily leave the state to deal with important requests. t Dv C2 The main difference between .Dv C1 and .Dv C2 lies in the internal hardware entry method of the processor. While less power is expected to be consumed than in .Dv C1 , the bus interface unit is still running. But depending on the processor, the local .Tn APIC timer may be stopped. Like with .Dv C1 , entering and exiting the state are expected to be fast operations. t Dv C3 This is the deepest conventional state. Parts of the .Tn CPU are actively powered down. The internal .Tn CPU clock is stopped. The local .Tn APIC timer is stopped. Depending on the processor, additional timers such as .Tn TSC
q time stamp counter may be stopped. Entry and exit latencies are expected to be high; the .Tn CPU can no longer .Dq quickly respond to bus activity or other interruptions. .El
p Each state has a latency associated with entry and exit. The higher the state, the lower the power consumption, and the higher the potential performance costs.
p The .Nm driver tries to balance the latency constraints when choosing the appropriate state. One of the checks involves bus master activity; if such activity is detected, a lower state is used. It is known that particularly .Xr usb 4 may cause high activity even when not in use. If maximum power savings are desirable, it may be necessary to use a custom kernel without .Tn USB support. And generally: to save power with C-states, one should avoid polling, both in userland and in the kernel. .Ss P-states The processor performance states, or P-states, are used to control the clock frequencies and voltages of a .Tn CPU . Underneath the abstractions of .Tn ACPI , P-states are associated with such technologies as .Dq SpeedStep
q Intel , .Dq PowerNow!
q Tn AMD , and .Dq PowerSaver
q VIA .
p The .Dv P0 state is always the highest operating frequency supported by the processor. The number of additional P-states may vary across processors and vendors. Each higher numbered P-state represents lower clock frequencies and hence lower power consumption.
p Unlike conventional .Tn CPU frequency management, .Tn ACPI provides support for Dynamic Frequency and Voltage Scaling
q Tn DVFS . This means that the firmware may request the implementation to dynamically scale the presently supported maximum clock frequency. For example, if .Xr acpiacad 4 is disconnected, the maximum available frequency may be lowered. Currently the .Nx implementation reacts to these events by imposing the dynamic maximum, but .Nm does not take any actions to manipulate the frequencies by itself. .Ss T-states Processor T-states, or .Dq throttling states , can be used to actively modulate the time a processor is allowed to execute. Outside the .Tn ACPI nomenclature, throttling may refer to .Dq on-demand clock modulation
q Tn ODCM , among others.
p The concept of .Dq duty cycle is relevant to T-states. It is generally defined to be a fraction of time that a system is in an .Dq active state. The T0-state has always a duty cycle of 100 %, and thus, comparable to the C0-state, the processor is fully active. Each additional higher-numbered T-state indicates lower duty cycles. At most eight T-states may be available, although also T-states use .Tn DVFS ; both the maximum and the minimum available T-state may change dynamically.
p The duty cycle does not refer to the actual clock signal, but to the time period in which the clock signal is allowed to drive the processor chip. For instance, if a T-state has a duty cycle of 75 %, the .Tn CPU runs at the same clock frequency and uses the same voltage, but 25 % of the time the .Tn CPU is forced to idle. Because of this, the use of T-states may severely reduce system performance.
p There are two typical situations for throttling: power management and thermal control. As a technique to save power, T-states are largely an artefact from the past. There was a short period in the x86 lineage when P-states were not yet available and throttling was considered as an option to modulate the processor power consumption. The approach was however quickly abandoned. In modern x86 systems P-states should be preferred in all circumstances. It is also more beneficial to move from the C0-state to deeper C-states than it is to actively force down the duty cycle of a processor.
p But T-states have retained their use as a last line of defence against critical thermal conditions. Many x86 processors include a catastrophic shutdown detector. When the processor core temperature reaches this factory defined trip-point, the processor execution is halted without any software control. Before this fatal condition, it is possible to use throttling for a short period of time in order to force the temperatures to lower levels. The thermal control modulation is typically started only when the system is in the highest-power P-state and a high temperature situation exists. After the temperatures have returned to non-critical levels, the modulation ceases. .Ss Statistics The .Nm driver uses event counters to track the times a processor has entered a given state. It is possible to view the statistics by using .Xr vmstat 1 (with the .Fl e flag). Note that valid per-CPU data is available only for C-states. .Ss System Control Variables The .Nm driver uses the same .Xr sysctl 8 controls for P-states as the ones provided by the kernel configuration .Xr options 4 .Dv ENHANCED_SPEEDSTEP and .Dv POWERNOW_K8 . Depending on the processor vendor, the second-level node is either c machdep.est or c machdep.powernow . Please note that future versions of .Nm may however remove the system control variables without further notice. .Sh SEE ALSO .Xr acpi 4 , .Xr acpitz 4 , .Xr cpu_idle 9 .Sh HISTORY The .Nm device driver appeared in .Nx 6.0 . .Sh AUTHORS .An Jukka Ruohonen .Aq jruohonen@iki.fi .Sh CAVEATS The .Nm driver should be considered experimental. At least the following caveats can be mentioned. l -bullet t It is currently only safe to use .Dv C1 on .Nx . All other C-states are disabled by default. t The .Tn AMD .Tn C1E extension is not supported. If this extension is available in a vendor .Tn BIOS , it is recommended to turn it off, with or without .Nm . t The use of native instructions in P-states is currently supported only on Intel .Tn CPUs . t Processor thermal control (see .Xr acpitz 4 ) is not yet supported. t There is currently neither a well-defined, machine-independent .Tn API for processor performance management nor a .Dq governor for different policies. It is only possible to control the .Tn CPU frequencies from userland. .El