lock.h revision 1.28
11.28Srmind/* $NetBSD: lock.h,v 1.28 2009/11/25 14:28:50 rmind Exp $ */ 21.1Sthorpej 31.1Sthorpej/*- 41.9Sthorpej * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 51.1Sthorpej * All rights reserved. 61.1Sthorpej * 71.1Sthorpej * This code is derived from software contributed to The NetBSD Foundation 81.1Sthorpej * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 91.1Sthorpej * NASA Ames Research Center. 101.1Sthorpej * 111.1Sthorpej * Redistribution and use in source and binary forms, with or without 121.1Sthorpej * modification, are permitted provided that the following conditions 131.1Sthorpej * are met: 141.1Sthorpej * 1. Redistributions of source code must retain the above copyright 151.1Sthorpej * notice, this list of conditions and the following disclaimer. 161.1Sthorpej * 2. Redistributions in binary form must reproduce the above copyright 171.1Sthorpej * notice, this list of conditions and the following disclaimer in the 181.1Sthorpej * documentation and/or other materials provided with the distribution. 191.1Sthorpej * 201.1Sthorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 211.1Sthorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 221.1Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 231.1Sthorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 241.1Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251.1Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261.1Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271.1Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281.1Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291.1Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 301.1Sthorpej * POSSIBILITY OF SUCH DAMAGE. 311.1Sthorpej */ 321.1Sthorpej 331.1Sthorpej/* 341.1Sthorpej * Machine-dependent spin lock operations. 351.1Sthorpej */ 361.1Sthorpej 371.4Sthorpej#ifndef _ALPHA_LOCK_H_ 381.4Sthorpej#define _ALPHA_LOCK_H_ 391.17Smartin 401.18She#ifdef _KERNEL_OPT 411.17Smartin#include "opt_multiprocessor.h" 421.18She#endif 431.4Sthorpej 441.25Sskrllstatic __inline int 451.25Sskrll__SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr) 461.25Sskrll{ 471.25Sskrll return *__ptr == __SIMPLELOCK_LOCKED; 481.25Sskrll} 491.25Sskrll 501.25Sskrllstatic __inline int 511.25Sskrll__SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr) 521.25Sskrll{ 531.25Sskrll return *__ptr == __SIMPLELOCK_UNLOCKED; 541.25Sskrll} 551.25Sskrll 561.25Sskrllstatic __inline void 571.25Sskrll__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr) 581.25Sskrll{ 591.25Sskrll *__ptr = __SIMPLELOCK_UNLOCKED; 601.25Sskrll} 611.25Sskrll 621.25Sskrllstatic __inline void 631.25Sskrll__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr) 641.25Sskrll{ 651.25Sskrll *__ptr = __SIMPLELOCK_LOCKED; 661.25Sskrll} 671.25Sskrll 681.22Sperrystatic __inline void 691.6Sthorpej__cpu_simple_lock_init(__cpu_simple_lock_t *alp) 701.4Sthorpej{ 711.4Sthorpej 721.21Sperry __asm volatile( 731.5Sthorpej "# BEGIN __cpu_simple_lock_init\n" 741.4Sthorpej " stl $31, %0 \n" 751.4Sthorpej " mb \n" 761.5Sthorpej " # END __cpu_simple_lock_init" 771.5Sthorpej : "=m" (*alp)); 781.4Sthorpej} 791.4Sthorpej 801.22Sperrystatic __inline void 811.6Sthorpej__cpu_simple_lock(__cpu_simple_lock_t *alp) 821.4Sthorpej{ 831.4Sthorpej unsigned long t0; 841.4Sthorpej 851.4Sthorpej /* 861.4Sthorpej * Note, if we detect that the lock is held when 871.4Sthorpej * we do the initial load-locked, we spin using 881.4Sthorpej * a non-locked load to save the coherency logic 891.4Sthorpej * some work. 901.4Sthorpej */ 911.4Sthorpej 921.21Sperry __asm volatile( 931.5Sthorpej "# BEGIN __cpu_simple_lock\n" 941.4Sthorpej "1: ldl_l %0, %3 \n" 951.4Sthorpej " bne %0, 2f \n" 961.4Sthorpej " bis $31, %2, %0 \n" 971.4Sthorpej " stl_c %0, %1 \n" 981.4Sthorpej " beq %0, 3f \n" 991.4Sthorpej " mb \n" 1001.4Sthorpej " br 4f \n" 1011.4Sthorpej "2: ldl %0, %3 \n" 1021.4Sthorpej " beq %0, 1b \n" 1031.4Sthorpej " br 2b \n" 1041.4Sthorpej "3: br 1b \n" 1051.4Sthorpej "4: \n" 1061.5Sthorpej " # END __cpu_simple_lock\n" 1071.16Sthorpej : "=&r" (t0), "=m" (*alp) 1081.16Sthorpej : "i" (__SIMPLELOCK_LOCKED), "m" (*alp) 1091.16Sthorpej : "memory"); 1101.4Sthorpej} 1111.4Sthorpej 1121.22Sperrystatic __inline int 1131.6Sthorpej__cpu_simple_lock_try(__cpu_simple_lock_t *alp) 1141.4Sthorpej{ 1151.4Sthorpej unsigned long t0, v0; 1161.4Sthorpej 1171.21Sperry __asm volatile( 1181.5Sthorpej "# BEGIN __cpu_simple_lock_try\n" 1191.4Sthorpej "1: ldl_l %0, %4 \n" 1201.4Sthorpej " bne %0, 2f \n" 1211.4Sthorpej " bis $31, %3, %0 \n" 1221.4Sthorpej " stl_c %0, %2 \n" 1231.4Sthorpej " beq %0, 3f \n" 1241.4Sthorpej " mb \n" 1251.4Sthorpej " bis $31, 1, %1 \n" 1261.4Sthorpej " br 4f \n" 1271.4Sthorpej "2: bis $31, $31, %1 \n" 1281.4Sthorpej " br 4f \n" 1291.4Sthorpej "3: br 1b \n" 1301.4Sthorpej "4: \n" 1311.5Sthorpej " # END __cpu_simple_lock_try" 1321.16Sthorpej : "=&r" (t0), "=r" (v0), "=m" (*alp) 1331.16Sthorpej : "i" (__SIMPLELOCK_LOCKED), "m" (*alp) 1341.16Sthorpej : "memory"); 1351.4Sthorpej 1361.7Ssimonb return (v0 != 0); 1371.4Sthorpej} 1381.4Sthorpej 1391.22Sperrystatic __inline void 1401.6Sthorpej__cpu_simple_unlock(__cpu_simple_lock_t *alp) 1411.4Sthorpej{ 1421.4Sthorpej 1431.21Sperry __asm volatile( 1441.5Sthorpej "# BEGIN __cpu_simple_unlock\n" 1451.9Sthorpej " mb \n" 1461.4Sthorpej " stl $31, %0 \n" 1471.5Sthorpej " # END __cpu_simple_unlock" 1481.5Sthorpej : "=m" (*alp)); 1491.4Sthorpej} 1501.11Sthorpej 1511.12Sthorpej#if defined(MULTIPROCESSOR) 1521.11Sthorpej/* 1531.11Sthorpej * On the Alpha, interprocessor interrupts come in at device priority 1541.11Sthorpej * level. This can cause some problems while waiting for r/w spinlocks 1551.11Sthorpej * from a high'ish priority level: IPIs that come in will not be processed. 1561.11Sthorpej * This can lead to deadlock. 1571.11Sthorpej * 1581.15Sthorpej * This hook allows IPIs to be processed while a spinlock's interlock 1591.11Sthorpej * is released. 1601.11Sthorpej */ 1611.15Sthorpej#define SPINLOCK_SPIN_HOOK \ 1621.11Sthorpejdo { \ 1631.11Sthorpej struct cpu_info *__ci = curcpu(); \ 1641.15Sthorpej int __s; \ 1651.11Sthorpej \ 1661.13Sthorpej if (__ci->ci_ipis != 0) { \ 1671.13Sthorpej /* printf("CPU %lu has IPIs pending\n", \ 1681.13Sthorpej __ci->ci_cpuid); */ \ 1691.28Srmind __s = splhigh(); \ 1701.13Sthorpej alpha_ipi_process(__ci, NULL); \ 1711.15Sthorpej splx(__s); \ 1721.13Sthorpej } \ 1731.11Sthorpej} while (0) 1741.23Sad#define SPINLOCK_BACKOFF_HOOK (void)nullop((void *)0) 1751.12Sthorpej#endif /* MULTIPROCESSOR */ 1761.4Sthorpej 1771.24Sadstatic __inline void 1781.23Sadmb_read(void) 1791.23Sad{ 1801.23Sad __asm __volatile("mb" : : : "memory"); 1811.23Sad} 1821.23Sad 1831.24Sadstatic __inline void 1841.23Sadmb_write(void) 1851.23Sad{ 1861.23Sad /* XXX wmb */ 1871.23Sad __asm __volatile("mb" : : : "memory"); 1881.23Sad} 1891.23Sad 1901.24Sadstatic __inline void 1911.23Sadmb_memory(void) 1921.23Sad{ 1931.23Sad __asm __volatile("mb" : : : "memory"); 1941.23Sad} 1951.23Sad 1961.4Sthorpej#endif /* _ALPHA_LOCK_H_ */ 197