cia_swiz_bus_mem.c revision 1.15 
1/* $NetBSD: cia_swiz_bus_mem.c,v 1.15 1997/09/02 13:19:22 thorpej Exp $ */
2
3/*
4 * Copyright (c) 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
22 *  School of Computer Science
23 *  Carnegie Mellon University
24 *  Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30#include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
31
32__KERNEL_RCSID(1, "$NetBSD: cia_swiz_bus_mem.c,v 1.15 1997/09/02 13:19:22 thorpej Exp $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>
37#include <sys/syslog.h>
38#include <sys/device.h>
39#include <vm/vm.h>
40
41#include <machine/bus.h>
42
43#include <alpha/pci/ciareg.h>
44#include <alpha/pci/ciavar.h>
45
46#define	CHIP		cia_swiz
47
48#define	CHIP_EX_MALLOC_SAFE(v)	(((struct cia_config *)(v))->cc_mallocsafe)
49#define	CHIP_D_MEM_EXTENT(v)	(((struct cia_config *)(v))->cc_d_mem_ex)
50#define	CHIP_S_MEM_EXTENT(v)	(((struct cia_config *)(v))->cc_s_mem_ex)
51
52/* Dense region 1 */
53#define	CHIP_D_MEM_W1_BUS_START(v)	0x00000000UL
54#define	CHIP_D_MEM_W1_BUS_END(v)	0xffffffffUL
55#define	CHIP_D_MEM_W1_SYS_START(v)	CIA_PCI_DENSE
56#define	CHIP_D_MEM_W1_SYS_END(v)	(CIA_PCI_DENSE + 0xffffffffUL)
57
58/* Sparse region 1 */
59#define	CHIP_S_MEM_W1_BUS_START(v)					\
60	    HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem)
61#define	CHIP_S_MEM_W1_BUS_END(v)					\
62	    (CHIP_S_MEM_W1_BUS_START(v) + HAE_MEM_REG1_MASK)
63#define	CHIP_S_MEM_W1_SYS_START(v)					\
64	    CIA_PCI_SMEM1
65#define	CHIP_S_MEM_W1_SYS_END(v)					\
66	    (CIA_PCI_SMEM1 + ((HAE_MEM_REG1_MASK + 1) << 5) - 1)
67
68/* Sparse region 2 */
69#define	CHIP_S_MEM_W2_BUS_START(v)					\
70	    HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem)
71#define	CHIP_S_MEM_W2_BUS_END(v)					\
72	    (CHIP_S_MEM_W2_BUS_START(v) + HAE_MEM_REG2_MASK)
73#define	CHIP_S_MEM_W2_SYS_START(v)					\
74	    CIA_PCI_SMEM2
75#define	CHIP_S_MEM_W2_SYS_END(v)					\
76	    (CIA_PCI_SMEM2 + ((HAE_MEM_REG2_MASK + 1) << 5) - 1)
77
78/* Sparse region 3 */
79#define	CHIP_S_MEM_W3_BUS_START(v)					\
80	    HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem)
81#define	CHIP_S_MEM_W3_BUS_END(v)					\
82	    (CHIP_S_MEM_W3_BUS_START(v) + HAE_MEM_REG3_MASK)
83#define	CHIP_S_MEM_W3_SYS_START(v)					\
84	    CIA_PCI_SMEM3
85#define	CHIP_S_MEM_W3_SYS_END(v)					\
86	    (CIA_PCI_SMEM3 + ((HAE_MEM_REG3_MASK + 1) << 5) - 1)
87
88#include <alpha/pci/pci_swiz_bus_mem_chipdep.c>
89