TODO revision 1.14.2.2
1 1.14.2.2 bouyer $NetBSD: TODO,v 1.14.2.2 2000/11/20 20:00:15 bouyer Exp $ 2 1.14.2.2 bouyer 3 1.14.2.2 bouyer To do list (not in any particular order). 4 1.14.2.2 bouyer 5 1.14.2.2 bouyer o XXX at least 2000/06/07 version is already quite unstable 6 1.14.2.2 bouyer on PICA and NEC Image RISCstation. (but almost OK on Magnum) 7 1.14.2.2 bouyer Userland commands dumps core randomly. 8 1.14.2.2 bouyer This version is before _MIPS_PADDR_T_64BIT changes 9 1.14.2.2 bouyer and MIPS3_TLB_WIRED_UPAGES changes. 10 1.14.2.2 bouyer 11 1.14.2.2 bouyer "vm_page_zero_enable = FALSE" makes this problem disappeared. 12 1.14.2.2 bouyer 13 1.14.2.2 bouyer currently, page zero in the idle loop is also disabled on 14 1.14.2.2 bouyer untested platforms like ESCstation rPC44/Tyne, SNI, Algorithmics 15 1.14.2.2 bouyer for safety. 16 1.14.2.2 bouyer 17 1.14.2.2 bouyer o XXX sudden hang up in a few minutes or dozens of minutes. 18 1.14.2.2 bouyer 2000 Mar 17 -current is OK. Mar 29 is NG. 19 1.14.2.2 bouyer 20 1.14.2.2 bouyer o Move the RO and WIRED attribute from the pte to the pv table. 21 1.14.2.2 bouyer This saves four instructions in the tlb miss handler. 22 1.14.2.2 bouyer 23 1.14.2.2 bouyer o Boot. Standalone boot program instead of booting the kernel directly. 24 1.14.2.2 bouyer 25 1.14.2.2 bouyer o Find out why bitmap load to S3-928 flashes screen. (X server) 26 1.14.2.2 bouyer Know why (enable linear mode). Need S3 info. 27 1.14.2.2 bouyer 28 1.14.2.2 bouyer o Can we have 32 double registers? 29 1.14.2.2 bouyer 30 1.14.2.2 bouyer o 64bit kernel/userland 31 1.14.2.2 bouyer 32 1.14.2.2 bouyer o NEC RISCstation 2200 support 33 1.14.2.2 bouyer 34 1.14.2.2 bouyer - framebuffer? 35 1.14.2.2 bouyer 36 1.14.2.2 bouyer - interrupt handling? 37 1.14.2.2 bouyer 38 1.14.2.2 bouyer o repair DeskStation support 39 1.14.2.2 bouyer 40 1.14.2.2 bouyer - requires bounce buffer bus_dma for Tyne 41 1.14.2.2 bouyer 42 1.14.2.2 bouyer - set up rPC44 wired TLB entries explicitly 43 1.14.2.2 bouyer 44 1.14.2.2 bouyer o repair Algor support 45 1.14.2.2 bouyer 46 1.14.2.2 bouyer - pci/pbcpcibus.c:vtophysaddr(): pbc_version < V96X_VREV_C0 case 47 1.14.2.2 bouyer 48 1.14.2.2 bouyer o sysinst 49 1.14.2.2 bouyer 50 1.14.2.2 bouyer o install notes 51 1.14.2.2 bouyer 52 1.14.2.2 bouyer o www: diskless HOW-TO port-arc specific part. 53 1.14.2.2 bouyer 54 1.14.2.2 bouyer o Xserver 55 1.14.2.2 bouyer 56 1.14.2.2 bouyer - VXL magnum, some RISCserver 2200 57 1.14.2.2 bouyer - vga/S3 pica, Image RISCstation - OpenBSD's? 58 1.14.2.2 bouyer - vga/cirrus some RISCserver 2200 59 1.14.2.2 bouyer - vga/??? DESKstation Tyne, rPC44 60 1.14.2.2 bouyer - TGA RISCserver 2250 61 1.14.2.2 bouyer 62 1.14.2.2 bouyer o X clients 63 1.14.2.2 bouyer probably pmax binary is good enough. 64 1.14.2.2 bouyer 65 1.14.2.2 bouyer o source code structure is quite obsolete, 66 1.14.2.2 bouyer general clean up is needed as nisimura-san suggested. 67 1.14.2.2 bouyer especially: 68 1.14.2.2 bouyer 69 1.14.2.2 bouyer - introduce struct platform and remove ugly ``switch (cputype)'' 70 1.14.2.2 bouyer in many places. 71 1.14.2.2 bouyer 72 1.14.2.2 bouyer - redesign interrupt handler framework to be flexible for 73 1.14.2.2 bouyer possible variations; must be sane and useful for R4030/R4230 74 1.14.2.2 bouyer 'local' devices and any combinations with ISA/EISA/PCI 75 1.14.2.2 bouyer 76 1.14.2.2 bouyer - remove inb/outb 77 1.14.2.2 bouyer 78 1.14.2.2 bouyer - try to interporate HZ; may be possible for R4030/R4230 system 79 1.14.2.2 bouyer or 'hardclock() by R4000' system. Clock resolution of 100Hz 80 1.14.2.2 bouyer without any interporation is substandard 81 1.14.2.2 bouyer 82 1.14.2.2 bouyer - remove UADDR 83 1.14.2.2 bouyer 84 1.14.2.2 bouyer o overblocking on interrupt handler, and related problems 85 1.14.2.2 bouyer 86 1.14.2.2 bouyer - SR_INT_IE should be enabled before calling hardclock(). 87 1.14.2.2 bouyer Since this is not done currently, spllowersoftclock() 88 1.14.2.2 bouyer on hardclock() doesn't have effect, and softclock() is 89 1.14.2.2 bouyer handled with all interrupt disabled in this case. 90 1.14.2.2 bouyer -> overblocking, possibly causes missing hardclock() 91 1.14.2.2 bouyer 92 1.14.2.2 bouyer - MIPS3_CLKF_BASEPRI() doesn't work correctly, 93 1.14.2.2 bouyer when MIPS_INT_MASK_5 (== MIPS_INT_MASK_CLOCK) is disabled. 94 1.14.2.2 bouyer -> micro optimization on hardclock() doesn't work. 95 1.14.2.2 bouyer but currently this may make hardclock() latency better 96 1.14.2.2 bouyer due to above SR_INT_IE problem. 97 1.14.2.2 bouyer s/MIPS_INT_MASK/MIPS3_INT_MASK/ makes this work, although tricky. 98 1.14.2.2 bouyer 99 1.14.2.2 bouyer - if (ipending & INT_MASK_REAL_DEV) == 0, 100 1.14.2.2 bouyer softnet() and softclock() are handled with all interrupt disabled. 101 1.14.2.2 bouyer -> overblocking, possibly causes missing hardclock() 102 1.14.2.2 bouyer 103 1.14.2.2 bouyer - softclock() is handled with softnet() disabled. 104 1.14.2.2 bouyer -> slightly overblocking 105 1.14.2.2 bouyer 106 1.14.2.2 bouyer - `netisr' handling in netintr() implies potential race condition. 107 1.14.2.2 bouyer `netisr' access should be protected by splnet(). 108 1.14.2.2 bouyer currently this is not real problem due to above overblocking. 109 1.14.2.2 bouyer 110 1.14.2.2 bouyer `ssir' handling on many mips ports has same problem. 111 1.14.2.2 bouyer It should be protected by splnet() or splserial() or splhigh() 112 1.14.2.2 bouyer (depends on the highest interrupt level which sets `ssir'). 113 1.14.2.2 bouyer Since `ssir' is accessed not only by setsoftnet() but also 114 1.14.2.2 bouyer by setsoft(), setsoftnet() should protect `ssir' by splserial() 115 1.14.2.2 bouyer or something. (i.e. priority level which setsoft() will be called) 116 1.14.2.2 bouyer Probably, it is better to split `ssir' variable for each 117 1.14.2.2 bouyer priority level. 118 1.14.2.2 bouyer also, _clearsoftintr() should be called before `ssir' access. 119 1.14.2.2 bouyer currently this is not real problem due to above overblocking. 120 1.14.2.2 bouyer 121 1.14.2.2 bouyer - INT_MASK_REAL_DEV should be removed 122 1.14.2.2 bouyer 123 1.14.2.2 bouyer - make CLKF_INTR() work. 124 1.14.2.2 bouyer 125 1.14.2.2 bouyer - major rework, possibly by software emulated spl. 126 1.14.2.2 bouyer splserial()/splsoftserial() 127 1.14.2.2 bouyer 128 1.14.2.2 bouyer o it is better to always disable MIPS_INT_MASK_CLOCK. 129 1.14.2.2 bouyer those are the points which should be fixed: 130 1.14.2.2 bouyer mips_idle: li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE) 131 1.14.2.2 bouyer machdep.c: curpcb->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; 132 1.14.2.2 bouyer spl0() 133 1.14.2.2 bouyer splnone() 134 1.14.2.2 bouyer 135 1.14.2.2 bouyer - MIPS_INT_MASK_CLOCK should be removed in someway 136 1.14.2.2 bouyer 137 1.14.2.2 bouyer o fix kernel start address 138 1.14.2.2 bouyer 139 1.14.2.2 bouyer o allocate PICA_TL_BASE and SONICBUF dynamically 140 1.14.2.2 bouyer 141 1.14.2.2 bouyer o merge new wscons 142 1.14.2.2 bouyer 143 1.14.2.2 bouyer o fix mem_clusters[] usage. 144 1.14.2.2 bouyer 145 1.14.2.2 bouyer o test and merge soren's clean up about proc0.p_addr. 146 1.14.2.2 bouyer 147 1.14.2.2 bouyer o parse ARC BIOS configuration information and use it 148 1.14.2.2 bouyer 149 1.14.2.2 bouyer o omit __BROKEN_CONFIG_UNIT_USAGE 150 1.14.2.2 bouyer 151 1.14.2.2 bouyer o omit __SWAP_BROKEN in <mips/types.h> 152 1.14.2.2 bouyer 153 1.14.2.2 bouyer o fix implementation of DELAY(), clean up clock implementation 154 1.14.2.2 bouyer 155 1.14.2.2 bouyer o increase MAXPHYS to 64KB 156 1.14.2.2 bouyer 157 1.14.2.2 bouyer o asc.c scsi clock/NCR53CF94 handling clean up 158 1.14.2.2 bouyer 159 1.14.2.2 bouyer o if_sn.c 160 1.14.2.2 bouyer 161 1.14.2.2 bouyer - ether address handling clean up 162 1.14.2.2 bouyer 163 1.14.2.2 bouyer - bus_dma'fy 164 1.14.2.2 bouyer - bus_space'fy 165 1.14.2.2 bouyer - split frontend and backend 166 1.14.2.2 bouyer - make this MI, and share with mac68k, newsmips/apbus 167 1.14.2.2 bouyer 168 1.14.2.2 bouyer o com_lbus.c clock handling clean up 169 1.14.2.2 bouyer 170 1.14.2.2 bouyer o intrcnt[] name cleanup 171 1.14.2.2 bouyer 172 1.14.2.2 bouyer o implement NCR 53c700(?) driver for NEC RISCserver 2200, 173 1.14.2.2 bouyer RISCstation 2200 and RISCstation 2250. 174 1.14.2.2 bouyer based on MI siop driver? 175 1.14.2.2 bouyer 176 1.14.2.2 bouyer o audio driver 177 1.14.2.2 bouyer 178 1.14.2.2 bouyer o use MI driver 179 1.14.2.2 bouyer 180 1.14.2.2 bouyer - use MI ncr53c9x driver instead of home grown asc 181 1.14.2.2 bouyer 182 1.14.2.2 bouyer - use MI bha driver instead of home grown btl 183 1.14.2.2 bouyer 184 1.14.2.2 bouyer - make fd driver MI, and share it with i386 185 1.14.2.2 bouyer (contact christos about MI fd driver) 186 1.14.2.2 bouyer 187 1.14.2.2 bouyer - make pccons MI, and share it with i386, 188 1.14.2.2 bouyer or simply eliminate pccons 189 1.14.2.2 bouyer 190 1.14.2.2 bouyer - LKM 191 1.14.2.2 bouyer 192 1.14.2.2 bouyer o ARC boot device name -> NetBSD root device conversion 193 1.14.2.2 bouyer 194 1.14.2.2 bouyer o and missing MI devices 195 1.14.2.2 bouyer ses?, lkm, vcoda, ... 196 1.14.2.2 bouyer 197 1.14.2.2 bouyer o bus_dmamap_sync: Hit_Invalidate and Hit_Write_Back cache operation 198 1.14.2.2 bouyer 199 1.14.2.2 bouyer o clean up ALEAF/NLEAF/NON_LEAF/NNON_LEAF in userland. 200 1.14.2.2 bouyer 201 1.14.2.2 bouyer o resolve "XXX" 202 1.14.2.2 bouyer 203 1.14.2.2 bouyer Lots of other things..... 204
Indexes created Sun Nov 02 07:10:05 GMT 2025