11.2Sandvar/* $NetBSD: eprtcreg.h,v 1.2 2022/03/24 12:12:00 andvar Exp $ */ 21.1Shamajima 31.1Shamajima/* 41.1Shamajima * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved. 51.1Shamajima * 61.1Shamajima * Redistribution and use in source and binary forms, with or without 71.1Shamajima * modification, are permitted provided that the following conditions 81.1Shamajima * are met: 91.1Shamajima * 1. Redistributions of source code must retain the above copyright 101.1Shamajima * notice, this list of conditions and the following disclaimer. 111.1Shamajima * 2. Redistributions in binary form must reproduce the above copyright 121.1Shamajima * notice, this list of conditions and the following disclaimer in the 131.1Shamajima * documentation and/or other materials provided with the distribution. 141.1Shamajima * 151.1Shamajima * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 161.1Shamajima * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 171.1Shamajima * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 181.1Shamajima * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 191.1Shamajima * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 201.1Shamajima * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 211.1Shamajima * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 221.1Shamajima * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 231.1Shamajima * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 241.1Shamajima * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 251.1Shamajima * SUCH DAMAGE. 261.1Shamajima */ 271.1Shamajima 281.1Shamajima/* Cirrus Logic EP9315 291.1Shamajima RealTime Clock register 301.1Shamajima http://www.cirrus.com/jp/pubs/manual/EP9315_Users_Guide.pdf */ 311.1Shamajima 321.1Shamajima#ifndef _EPRTCREG_H_ 331.1Shamajima#define _EPRTCREG_H_ 341.1Shamajima 351.1Shamajima#define EP93XX_RTC_Data 0x00 /* RTC Data Register (RO) */ 361.1Shamajima#define EP93XX_RTC_Match 0x04 /* RTC Match Register (R/W) */ 371.1Shamajima#define EP93XX_RTC_Sts 0x08 /* RTC Status/EOI Register (R/W) */ 381.1Shamajima#define EP93XX_RTC_INTR (1<<0) /* Interrupt status */ 391.1Shamajima#define EP93XX_RTC_Load 0x0c /* RTC Load Register (R/W) */ 401.1Shamajima#define EP93XX_RTC_Ctrl 0x10 /* RTC Control Register (R/W) */ 411.1Shamajima#define EP93XX_RTC_MIE (1<<0) /* Match Interrupt Enable */ 421.2Sandvar#define EP93XX_RTC_SWComp 0x108 /* RTC Software Compensation (R/W) */ 431.1Shamajima#define EP93XX_RTC_DEL_SHIFT (1<<16) /* Number of clocks to delete */ 441.1Shamajima#define EP93XX_RTC_DEL_MASK 0x001f0000 451.2Sandvar#define EP93XX_RTC_INT_SHIFT (1<<0) /* Counter pre-load Integer value */ 461.1Shamajima#define EP93XX_RTC_INT_MASK 0x0000ffff 471.1Shamajima 481.1Shamajima#endif /* _EPRTCREG_H_ */ 49