11.2Sbsh/* $NetBSD: imxkppreg.h,v 1.2 2010/11/30 13:05:27 bsh Exp $ */ 21.1Sbsh 31.1Sbsh/* 41.1Sbsh * Copyright (c) 2010 Genetec Corporation. All rights reserved. 51.1Sbsh * Written by Hiroyuki Bessho for Genetec Corporation. 61.1Sbsh * 71.1Sbsh * Redistribution and use in source and binary forms, with or without 81.1Sbsh * modification, are permitted provided that the following conditions 91.1Sbsh * are met: 101.1Sbsh * 1. Redistributions of source code must retain the above copyright 111.1Sbsh * notice, this list of conditions and the following disclaimer. 121.1Sbsh * 2. Redistributions in binary form must reproduce the above copyright 131.1Sbsh * notice, this list of conditions and the following disclaimer in the 141.1Sbsh * documentation and/or other materials provided with the distribution. 151.1Sbsh * 161.1Sbsh * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 171.1Sbsh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 181.1Sbsh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 191.1Sbsh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 201.1Sbsh * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 211.1Sbsh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 221.1Sbsh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 231.1Sbsh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 241.1Sbsh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 251.1Sbsh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 261.1Sbsh * POSSIBILITY OF SUCH DAMAGE. 271.1Sbsh */ 281.1Sbsh 291.1Sbsh/* 301.1Sbsh * Register definitions for Keypad Port (KPP) 311.1Sbsh */ 321.1Sbsh 331.1Sbsh#ifndef _ARM_IMX_IMXKPPREG_H 341.1Sbsh#define _ARM_IMX_IMXKPPREG_H 351.1Sbsh 361.1Sbsh/* Registers are byte- or halfword-addressable */ 371.1Sbsh 381.1Sbsh#define KPP_KPCR 0x0000 /* control register */ 391.1Sbsh#define KPCR_KCO 0xff00 /* Column strobe */ 401.1Sbsh#define KPCR_KRE 0x00ff /* Row Enable */ 411.1Sbsh#define KPP_KPSR 0x0002 /* status register */ 421.1Sbsh#define KPSR_KRIE __BIT(9) 431.1Sbsh#define KPSR_KDIE __BIT(8) 441.1Sbsh#define KPSR_KRSS __BIT(3) 451.1Sbsh#define KPSR_KDSC __BIT(2) 461.1Sbsh#define KPSR_KPKR __BIT(1) 471.1Sbsh#define KPSR_KPKD __BIT(0) 481.1Sbsh 491.1Sbsh#define KPP_KDDR 0x0004 /* data direction register */ 501.1Sbsh 511.1Sbsh#define KPP_KPDR 0x0006 /* data register */ 521.1Sbsh 531.2Sbsh#define KPP_SIZE 0x0008 541.2Sbsh 551.1Sbsh#endif /* _ARM_IMX_IMXKPPREG_H */ 56