imx8mq_usbphy.c revision 1.2 
1/* $NetBSD: imx8mq_usbphy.c,v 1.2 2021/01/18 02:35:48 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31__KERNEL_RCSID(0, "$NetBSD: imx8mq_usbphy.c,v 1.2 2021/01/18 02:35:48 thorpej Exp $");
32
33#include <sys/param.h>
34#include <sys/bus.h>
35#include <sys/device.h>
36#include <sys/intr.h>
37#include <sys/systm.h>
38#include <sys/time.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	PHY_CTL0_ADDR		0x00
43#define	 REF_SSP_EN		__BIT(2)
44
45#define	PHY_CTL1_ADDR		0x04
46#define	 PHY_VDATDATENB0	__BIT(20)
47#define	 PHY_VDATSRCENB0	__BIT(19)
48#define	 PHY_ATERESET		__BIT(3)
49#define	 PHY_COMMONONN		__BIT(1)
50#define	 PHY_RESET		__BIT(0)
51
52#define	PHY_CTL2_ADDR		0x08
53#define	 PHY_TXENABLEN0		__BIT(8)
54
55static int imx8mq_usbphy_match(device_t, cfdata_t, void *);
56static void imx8mq_usbphy_attach(device_t, device_t, void *);
57
58static const struct device_compatible_entry compat_data[] = {
59	{ .compat = "fsl,imx8mq-usb-phy" },
60
61	{ 0 }
62};
63
64struct imx8mq_usbphy_softc {
65	device_t		sc_dev;
66	bus_space_tag_t		sc_bst;
67	bus_space_handle_t	sc_bsh;
68	int			sc_phandle;
69};
70
71#define	PHY_READ(sc, reg)				\
72	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
73#define	PHY_WRITE(sc, reg, val)			\
74	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
75
76CFATTACH_DECL_NEW(imx8mqusbphy, sizeof(struct imx8mq_usbphy_softc),
77	imx8mq_usbphy_match, imx8mq_usbphy_attach, NULL, NULL);
78
79static void *
80imx8mq_usbphy_acquire(device_t dev, const void *data, size_t len)
81{
82	if (len != 0)
83		return NULL;
84
85	return (void *)(uintptr_t)1;
86}
87
88static void
89imx8mq_usbphy_release(device_t dev, void *priv)
90{
91}
92
93static int
94imx8mq_usbphy_enable(device_t dev, void *priv, bool enable)
95{
96	struct imx8mq_usbphy_softc * const sc = device_private(dev);
97	struct fdtbus_regulator *reg;
98	uint32_t val;
99	int error;
100
101	if (enable) {
102		if (of_hasprop(sc->sc_phandle, "vbus-supply")) {
103			reg = fdtbus_regulator_acquire(sc->sc_phandle, "vbus-supply");
104			if (reg != NULL) {
105				error = fdtbus_regulator_enable(reg);
106				if (error != 0)
107					device_printf(dev, "WARNING: couldn't enable vbus-supply: %d\n", error);
108			} else {
109				device_printf(dev, "WARNING: couldn't acquire vbus-supply\n");
110			}
111		}
112
113		val = PHY_READ(sc, PHY_CTL1_ADDR);
114		val &= ~PHY_VDATDATENB0;
115		val &= ~PHY_VDATSRCENB0;
116		val &= ~PHY_COMMONONN;
117		val |= PHY_RESET;
118		val |= PHY_ATERESET;
119		PHY_WRITE(sc, PHY_CTL1_ADDR, val);
120
121		val = PHY_READ(sc, PHY_CTL0_ADDR);
122		val |= REF_SSP_EN;
123		PHY_WRITE(sc, PHY_CTL0_ADDR, val);
124
125		val = PHY_READ(sc, PHY_CTL2_ADDR);
126		val |= PHY_TXENABLEN0;
127		PHY_WRITE(sc, PHY_CTL2_ADDR, val);
128
129		val = PHY_READ(sc, PHY_CTL1_ADDR);
130		val &= ~PHY_RESET;
131		val &= ~PHY_ATERESET;
132		PHY_WRITE(sc, PHY_CTL1_ADDR, val);
133	}
134
135	return 0;
136}
137
138const struct fdtbus_phy_controller_func imx8mq_usbphy_funcs = {
139	.acquire = imx8mq_usbphy_acquire,
140	.release = imx8mq_usbphy_release,
141	.enable = imx8mq_usbphy_enable,
142};
143
144static int
145imx8mq_usbphy_match(device_t parent, cfdata_t cf, void *aux)
146{
147	struct fdt_attach_args * const faa = aux;
148
149	return of_match_compat_data(faa->faa_phandle, compat_data);
150}
151
152static void
153imx8mq_usbphy_attach(device_t parent, device_t self, void *aux)
154{
155	struct imx8mq_usbphy_softc * const sc = device_private(self);
156	struct fdt_attach_args * const faa = aux;
157	const int phandle = faa->faa_phandle;
158	bus_addr_t addr;
159	bus_size_t size;
160
161	sc->sc_dev = self;
162	sc->sc_bst = faa->faa_bst;
163	sc->sc_phandle = phandle;
164
165	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
166		aprint_error(": couldn't get registers\n");
167		return;
168	}
169	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
170		aprint_error(": couldn't map registers\n");
171		return;
172	}
173
174	/* Enable clocks */
175	fdtbus_clock_assign(phandle);
176	if (fdtbus_clock_enable(phandle, "phy", true) != 0) {
177		aprint_error(": couldn't enable phy clock\n");
178		return;
179	}
180
181	aprint_naive("\n");
182	aprint_normal(": USB PHY\n");
183
184	fdtbus_register_phy_controller(self, phandle, &imx8mq_usbphy_funcs);
185}
186