intr.h revision 1.2
1/* $NetBSD: intr.h,v 1.2 1997/11/27 10:18:47 sakamoto Exp $ */ 2/* $OpenBSD: intr.h,v 1.1 1997/10/13 10:53:45 pefo Exp $ */ 3 4/* 5 * Copyright (c) 1996, 1997 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef _BEBOX_INTR_H_ 34#define _BEBOX_INTR_H_ 35 36/* Interrupt priority `levels'. */ 37#define IPL_NONE 9 /* nothing */ 38#define IPL_SOFTCLOCK 8 /* software clock interrupt */ 39#define IPL_SOFTNET 7 /* software network interrupt */ 40#define IPL_BIO 6 /* block I/O */ 41#define IPL_NET 5 /* network */ 42#define IPL_TTY 4 /* terminal */ 43#define IPL_IMP 3 /* memory allocation */ 44#define IPL_AUDIO 2 /* audio */ 45#define IPL_CLOCK 1 /* clock */ 46#define IPL_HIGH 0 /* everything */ 47#define NIPL 10 48 49/* Interrupt sharing types. */ 50#define IST_NONE 0 /* none */ 51#define IST_PULSE 1 /* pulsed */ 52#define IST_EDGE 2 /* edge-triggered */ 53#define IST_LEVEL 3 /* level-triggered */ 54 55#ifndef _LOCORE 56 57/* 58 * Interrupt handler chains. intr_establish() inserts a handler into 59 * the list. The handler is called with its (single) argument. 60 */ 61struct intrhand { 62 int (*ih_fun) __P((void *)); 63 void *ih_arg; 64 u_long ih_count; 65 struct intrhand *ih_next; 66 int ih_level; 67 int ih_irq; 68}; 69 70void setsoftclock __P((void)); 71void clearsoftclock __P((void)); 72int splsoftclock __P((void)); 73void setsoftnet __P((void)); 74void clearsoftnet __P((void)); 75int splsoftnet __P((void)); 76 77void do_pending_int __P((void)); 78 79 80extern volatile int cpl, ipending, astpending, tickspending; 81extern int imask[]; 82 83/* 84 * Reorder protection in the following inline functions is 85 * achived with the "eieio" instruction which the assembler 86 * seems to detect and then doen't move instructions past.... 87 */ 88static __inline int 89splraise(newcpl) 90 int newcpl; 91{ 92 int oldcpl; 93 94 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 95 oldcpl = cpl; 96 cpl = oldcpl | newcpl; 97 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 98 return(oldcpl); 99} 100 101static __inline void 102splx(newcpl) 103 int newcpl; 104{ 105 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 106 cpl = newcpl; 107 if(ipending & ~newcpl) 108 do_pending_int(); 109 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 110} 111 112static __inline int 113spllower(newcpl) 114 int newcpl; 115{ 116 int oldcpl; 117 118 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 119 oldcpl = cpl; 120 cpl = newcpl; 121 if(ipending & ~newcpl) 122 do_pending_int(); 123 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 124 return(oldcpl); 125} 126 127/* Following code should be implemented with lwarx/stwcx to avoid 128 * the disable/enable. i need to read the manual once more.... */ 129static __inline void 130set_sint(pending) 131 int pending; 132{ 133 int msrsave; 134 135 __asm__ ("mfmsr %0" : "=r"(msrsave)); 136 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 137 ipending |= pending; 138 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 139} 140 141#define ICU_LEN 32 142#define IRQ_SLAVE 2 143#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 144 145#define MOTHER_BOARD_REG 0x7ffff000 146#define CPU0_INT_MASK 0x0f0 147#define CPU1_INT_MASK 0x1f0 148#define INT_STATE_REG 0x2f0 149 150#define SINT_CLOCK 0x10000000 151#define SINT_NET 0x20000000 152#define SINT_TTY 0x40000000 153#define SPL_CLOCK 0x80000000 154#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_TTY) 155 156#define CNT_SINT_NET 29 157#define CNT_SINT_CLOCK 30 158#define CNT_CLOCK 31 159 160#define splbio() splraise(imask[IPL_BIO]) 161#define splnet() splraise(imask[IPL_NET]) 162#define spltty() splraise(imask[IPL_TTY]) 163#define splclock() splraise(SPL_CLOCK|SINT_CLOCK|SINT_NET) 164#define splimp() splraise(imask[IPL_IMP]) 165#define splstatclock() splhigh() 166#define splsoftclock() spllower(SINT_CLOCK) 167#define splsoftnet() splraise(SINT_NET) 168#define splsofttty() splraise(SINT_TTY) 169 170#define setsoftclock() set_sint(SINT_CLOCK); 171#define setsoftnet() set_sint(SINT_NET); 172#define setsofttty() set_sint(SINT_TTY); 173 174#define splhigh() splraise(0xffffffff) 175#define spl0() spllower(0) 176 177#endif /* !_LOCORE */ 178 179#endif /* !_BEBOX_INTR_H_ */ 180