intr.h revision 1.5
1/* $NetBSD: intr.h,v 1.5 1998/07/18 21:27:27 is Exp $ */ 2/* $OpenBSD: intr.h,v 1.1 1997/10/13 10:53:45 pefo Exp $ */ 3 4/* 5 * Copyright (c) 1996, 1997 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef _BEBOX_INTR_H_ 34#define _BEBOX_INTR_H_ 35 36/* Interrupt priority `levels'. */ 37#define IPL_NONE 9 /* nothing */ 38#define IPL_SOFTCLOCK 8 /* software clock interrupt */ 39#define IPL_SOFTNET 7 /* software network interrupt */ 40#define IPL_BIO 6 /* block I/O */ 41#define IPL_NET 5 /* network */ 42#define IPL_TTY 4 /* terminal */ 43#define IPL_IMP 3 /* memory allocation */ 44#define IPL_AUDIO 2 /* audio */ 45#define IPL_CLOCK 1 /* clock */ 46#define IPL_HIGH 0 /* everything */ 47#define IPL_SERIAL 0 /* serial */ 48#define NIPL 10 49 50/* Interrupt sharing types. */ 51#define IST_NONE 0 /* none */ 52#define IST_PULSE 1 /* pulsed */ 53#define IST_EDGE 2 /* edge-triggered */ 54#define IST_LEVEL 3 /* level-triggered */ 55 56#ifndef _LOCORE 57 58/* 59 * Interrupt handler chains. intr_establish() inserts a handler into 60 * the list. The handler is called with its (single) argument. 61 */ 62struct intrhand { 63 int (*ih_fun) __P((void *)); 64 void *ih_arg; 65 u_long ih_count; 66 struct intrhand *ih_next; 67 int ih_level; 68 int ih_irq; 69}; 70 71void setsoftclock __P((void)); 72void clearsoftclock __P((void)); 73int splsoftclock __P((void)); 74void setsoftnet __P((void)); 75void clearsoftnet __P((void)); 76int splsoftnet __P((void)); 77 78void do_pending_int __P((void)); 79 80 81extern volatile int cpl, ipending, astpending, tickspending; 82extern int imask[]; 83 84/* 85 * Reorder protection in the following inline functions is 86 * achived with the "eieio" instruction which the assembler 87 * seems to detect and then doen't move instructions past.... 88 */ 89static __inline int 90splraise(newcpl) 91 int newcpl; 92{ 93 int oldcpl; 94 95 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 96 oldcpl = cpl; 97 cpl = oldcpl | newcpl; 98 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 99 return(oldcpl); 100} 101 102static __inline void 103splx(newcpl) 104 int newcpl; 105{ 106 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 107 cpl = newcpl; 108 if(ipending & ~newcpl) 109 do_pending_int(); 110 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 111} 112 113static __inline int 114spllower(newcpl) 115 int newcpl; 116{ 117 int oldcpl; 118 119 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 120 oldcpl = cpl; 121 cpl = newcpl; 122 if(ipending & ~newcpl) 123 do_pending_int(); 124 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 125 return(oldcpl); 126} 127 128/* Following code should be implemented with lwarx/stwcx to avoid 129 * the disable/enable. i need to read the manual once more.... */ 130static __inline void 131set_sint(pending) 132 int pending; 133{ 134 int msrsave; 135 136 __asm__ ("mfmsr %0" : "=r"(msrsave)); 137 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 138 ipending |= pending; 139 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 140} 141 142#define ICU_LEN 32 143#define IRQ_SLAVE 2 144#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 145 146#define MOTHER_BOARD_REG 0x7ffff000 147#define CPU0_INT_MASK 0x0f0 148#define CPU1_INT_MASK 0x1f0 149#define INT_STATE_REG 0x2f0 150 151#define SINT_CLOCK 0x20000000 152#define SINT_NET 0x40000000 153#define SINT_SERIAL 0x80000000 154#define SPL_CLOCK 0x00000001 155#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 156 157#define CNT_SINT_NET 29 158#define CNT_SINT_CLOCK 30 159#define CNT_SINT_SERIAL 31 160#define CNT_CLOCK 0 161 162#define splbio() splraise(imask[IPL_BIO]) 163#define splnet() splraise(imask[IPL_NET]) 164#define spltty() splraise(imask[IPL_TTY]) 165#define splclock() splraise(SPL_CLOCK|SINT_CLOCK|SINT_NET) 166#define splimp() splraise(imask[IPL_IMP]) 167#define splserial() splraise(imask[IPL_SERIAL]) 168#define splstatclock() splhigh() 169#define splsoftclock() spllower(SINT_CLOCK) 170#define splsoftnet() splraise(SINT_NET) 171#define splsoftserial() splraise(SINT_SERIAL) 172 173#define spllpt() spltty() 174 175#define setsoftclock() set_sint(SINT_CLOCK); 176#define setsoftnet() set_sint(SINT_NET); 177#define setsoftserial() set_sint(SINT_SERIAL); 178 179#define splhigh() splraise(0xffffffff) 180#define spl0() spllower(0) 181 182#endif /* !_LOCORE */ 183 184#endif /* !_BEBOX_INTR_H_ */ 185