smdk2410_start.S revision 1.3 
1/*	$NetBSD: smdk2410_start.S,v 1.3 2003/08/29 12:07:33 bsh Exp $ */
2
3/*
4 * Copyright (c) 2002, 2003 Fujitsu Component Limited
5 * Copyright (c) 2002, 2003 Genetec Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 *    Genetec corporation may not be used to endorse or promote products
18 *    derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#include <machine/asm.h>
36#include <arm/armreg.h>
37#include <arm/arm32/pte.h>
38#include <arm/arm32/pmap.h>		/* for PMAP_DOMAIN_KERNEL */
39
40#include <arm/s3c2xx0/s3c2410reg.h>	/* for S3C2410_SDRAM_START */
41
42/*
43 * Kernel start routine for Samsung SMDK2410.
44 * This code is excuted at the very first after the kernel is loaded
45 * by boot program.
46 */
47	.text
48
49#ifndef	SDRAM_START
50#define	SDRAM_START	S3C2410_SDRAM_START
51#endif
52#define KERNEL_TEXT_ADDR	(SDRAM_START+0x00200000)
53
54	.global	_C_LABEL(smdk2410_start)
55_C_LABEL(smdk2410_start):
56	/* Disable interrupt */
57	mrs	r0, cpsr
58	orr	r0, r0, #I32_bit
59	msr	cpsr, r0
60
61	/* Are we running on right place ? */
62	adr r0, _C_LABEL(smdk2410_start)
63	ldr	r2, =KERNEL_TEXT_ADDR
64	cmp	r0, r2
65	beq	smdk2410_start_ram
66
67	/*
68	 * move me to RAM
69	 */
70	ldr r1, Lcopy_size
71	adr r0, _C_LABEL(smdk2410_start)
72	add r1, r1, #3
73	mov r1, r1, LSR #2
74	mov r4, r2
75
76	cmp r0, r2
77	bhs 5f
78
79	/* src < dest. copy from top */
80	add r0,r0,r1,LSL #2
81	add r2,r2,r1,LSL #2
82
833:	ldr r3,[r0,#-4]!
84	str r3,[r2,#-4]!
85	subs r1,r1,#1
86	bhi 3b
87	b 7f
88
89	/* src >= dest. copy from bottom */
905:	ldr r3,[r0],#4
91	str r3,[r2],#4
92	subs r1,r1,#1
93	bhi 5b
94
957:
96	/* Jump to RAM */
97	ldr r0, Lstart_off
98	add pc, r4, r0
99
100Lcopy_size:	.word _edata-_C_LABEL(smdk2410_start)
101Lstart_off:	.word smdk2410_start_ram-_C_LABEL(smdk2410_start)
102
103smdk2410_start_ram:
104	/*
105	 *  Kernel is loaded in SDRAM (0x30200000..), and is expected to run
106	 *  in VA 0xc0200000..
107	 */
108
109	/* Disable MMU for a while */
110	mrc	p15, 0, r2, c1, c0, 0
111	bic	r2, r2, #CPU_CONTROL_MMU_ENABLE
112	mcr	p15, 0, r2, c1, c0, 0
113
114	nop
115	nop
116	nop
117
118	mov	r0,#SDRAM_START      /* pagetable */
119	adr	r4, mmu_init_table
120	b	2f
1211:
122	str	r3, [r0, r2]
123	add	r2, r2, #4
124	add	r3, r3, #(L1_S_SIZE)
125	adds	r1, r1, #-1
126	bhi	1b
1272:
128	ldmia	r4!, {r1,r2,r3}   /* # of sections, PA|attr, VA */
129	cmp	r1, #0
130	bne	1b
131
132	mcr	p15, 0, r0, c2, c0, 0	/* Set TTB */
133	mcr	p15, 0, r0, c8, c7, 0	/* Flush TLB */
134
135	/* Set the Domain Access register.  Very important! */
136	mov	r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
137	mcr	p15, 0, r0, c3, c0, 0
138
139	/* Enable MMU */
140	mrc	p15, 0, r0, c1, c0, 0
141	orr	r0, r0, #CPU_CONTROL_MMU_ENABLE
142	mcr	p15, 0, r0, c1, c0, 0
143
144	nop
145	nop
146	nop
147
148	/* Jump to kernel code in TRUE VA */
149	adr	r0, Lstart
150	ldr	pc, [r0]
151
152Lstart:
153	.word	start
154
155#define MMU_INIT(va,pa,n_sec,attr) \
156	.word	n_sec					    ; \
157	.word	4*((va)>>L1_S_SHIFT)			    ; \
158	.word	(pa)|(attr)				    ;
159
160mmu_init_table:
161	/* fill all table VA==PA */
162	MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
163	/* map SDRAM VA==PA, WT cacheable */
164	MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
165	/* map VA 0xc0000000..0xc3ffffff to PA 0x30000000..0x33ffffff */
166	MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
167
168	.word 0	/* end of table */
169
170