intr.h revision 1.4
1/* $NetBSD: intr.h,v 1.4 2003/04/01 17:34:10 hpeyerl Exp $ */ 2 3/*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _EVBMIPS_INTR_H_ 40#define _EVBMIPS_INTR_H_ 41 42#include <sys/device.h> 43#include <sys/lock.h> 44#include <sys/queue.h> 45 46#define IPL_NONE 0 /* disable only this interrupt */ 47 48#define IPL_SOFT 1 /* generic software interrupts */ 49#define IPL_SOFTCLOCK 2 /* clock software interrupts */ 50#define IPL_SOFTNET 3 /* network software interrupts */ 51#define IPL_SOFTSERIAL 4 /* serial software interrupts */ 52 53#define IPL_BIO 5 /* disable block I/O interrupts */ 54#define IPL_NET 6 /* disable network interrupts */ 55#define IPL_TTY 7 /* disable terminal interrupts */ 56#define IPL_SERIAL 7 /* disable serial interrupts */ 57#define IPL_CLOCK 8 /* disable clock interrupts */ 58#define IPL_HIGH 8 /* disable all interrupts */ 59 60#define _IPL_NSOFT 4 /* max soft IPL + 1 */ 61#define _IPL_N 9 /* max IPL + 1 */ 62 63#define _IPL_SI0_FIRST IPL_SOFT 64#define _IPL_SI0_LAST IPL_SOFTCLOCK 65 66#define _IPL_SI1_FIRST IPL_SOFTNET 67#define _IPL_SI1_LAST IPL_SOFTSERIAL 68 69#define IPL_SOFTNAMES { \ 70 "misc", \ 71 "clock", \ 72 "net", \ 73 "serial", \ 74} 75 76#define IST_UNUSABLE -1 /* interrupt cannot be used */ 77#define IST_NONE 0 /* none (dummy) */ 78#define IST_PULSE 1 /* pulsed */ 79#define IST_EDGE 2 /* edge-triggered */ 80#define IST_LEVEL 3 /* level-triggered */ 81#define IST_LEVEL_HIGH 4 /* level triggered, active high */ 82#define IST_LEVEL_LOW 5 /* level triggered, active low */ 83 84#ifdef _KERNEL 85 86extern const u_int32_t ipl_sr_bits[_IPL_N]; 87extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT]; 88 89extern int _splraise(int); 90extern int _spllower(int); 91extern int _splset(int); 92extern int _splget(int); 93extern int _splnone(int); 94extern int _setsoftintr(int); 95extern int _clrsoftintr(int); 96 97#define splhigh() _splraise(ipl_sr_bits[IPL_HIGH]) 98#define spl0() (void) _spllower(0) 99#define splx(s) (void) _splset(s) 100#define splbio() _splraise(ipl_sr_bits[IPL_BIO]) 101#define splnet() _splraise(ipl_sr_bits[IPL_NET]) 102#define spltty() _splraise(ipl_sr_bits[IPL_TTY]) 103#define splserial() _splraise(ipl_sr_bits[IPL_SERIAL]) 104#define splvm() spltty() 105#define splclock() _splraise(ipl_sr_bits[IPL_CLOCK]) 106#define splstatclock() splclock() 107 108#define splsched() splclock() 109#define spllock() splhigh() 110#define spllpt() spltty() 111 112#define splsoft() _splraise(ipl_sr_bits[IPL_SOFT]) 113#define splsoftclock() _splraise(ipl_sr_bits[IPL_SOFTCLOCK]) 114#define splsoftnet() _splraise(ipl_sr_bits[IPL_SOFTNET]) 115#define splsoftserial() _splraise(ipl_sr_bits[IPL_SOFTSERIAL]) 116 117#define spllowersoftclock() _spllower(ipl_sr_bits[IPL_SOFTCLOCK]) 118 119struct evbmips_intrhand { 120 LIST_ENTRY(evbmips_intrhand) ih_q; 121 int (*ih_func)(void *); 122 void *ih_arg; 123 int ih_irq; 124}; 125 126#define setsoft(x) \ 127do { \ 128 _setsoftintr(ipl_si_to_sr[(x) - IPL_SOFT]); \ 129} while (0) 130 131struct evbmips_soft_intrhand { 132 TAILQ_ENTRY(evbmips_soft_intrhand) 133 sih_q; 134 struct evbmips_soft_intr *sih_intrhead; 135 void (*sih_fn)(void *); 136 void *sih_arg; 137 int sih_pending; 138}; 139 140struct evbmips_soft_intr { 141 TAILQ_HEAD(, evbmips_soft_intrhand) 142 softintr_q; 143 struct evcnt softintr_evcnt; 144 struct simplelock softintr_slock; 145 unsigned long softintr_ipl; 146}; 147 148void *softintr_establish(int, void (*)(void *), void *); 149void softintr_disestablish(void *); 150void softintr_init(void); 151 152#define softintr_schedule(arg) \ 153do { \ 154 struct evbmips_soft_intrhand *__sih = (arg); \ 155 struct evbmips_soft_intr *__si = __sih->sih_intrhead; \ 156 int __s; \ 157 \ 158 __s = splhigh(); \ 159 simple_lock(&__si->softintr_slock); \ 160 if (__sih->sih_pending == 0) { \ 161 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 162 __sih->sih_pending = 1; \ 163 setsoft(__si->softintr_ipl); \ 164 } \ 165 simple_unlock(&__si->softintr_slock); \ 166 splx(__s); \ 167} while (0) 168 169/* XXX For legacy software interrupts. */ 170extern struct evbmips_soft_intrhand *softnet_intrhand; 171 172#define setsoftnet() softintr_schedule(softnet_intrhand) 173 174void evbmips_intr_init(void); 175void intr_init(void); 176void evbmips_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 177void *evbmips_intr_establish(int, int (*)(void *), void *); 178void evbmips_intr_disestablish(void *); 179#endif /* _KERNEL */ 180#endif /* ! _EVBMIPS_INTR_H_ */ 181