11.3Sandvar/* $NetBSD: machdep.c,v 1.3 2021/09/19 11:37:00 andvar Exp $ */ 21.1Srin 31.1Srin/* 41.1Srin * Taken from src/sys/arch/evbppc/walnut/machdep.c: 51.1Srin * NetBSD: machdep.c,v 1.67 2021/03/30 05:08:16 rin Exp 61.1Srin */ 71.1Srin 81.1Srin/* 91.1Srin * Copyright 2001, 2002 Wasabi Systems, Inc. 101.1Srin * All rights reserved. 111.1Srin * 121.1Srin * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 131.1Srin * 141.1Srin * Redistribution and use in source and binary forms, with or without 151.1Srin * modification, are permitted provided that the following conditions 161.1Srin * are met: 171.1Srin * 1. Redistributions of source code must retain the above copyright 181.1Srin * notice, this list of conditions and the following disclaimer. 191.1Srin * 2. Redistributions in binary form must reproduce the above copyright 201.1Srin * notice, this list of conditions and the following disclaimer in the 211.1Srin * documentation and/or other materials provided with the distribution. 221.1Srin * 3. All advertising materials mentioning features or use of this software 231.1Srin * must display the following acknowledgement: 241.1Srin * This product includes software developed for the NetBSD Project by 251.1Srin * Wasabi Systems, Inc. 261.1Srin * 4. The name of Wasabi Systems, Inc. may not be used to endorse 271.1Srin * or promote products derived from this software without specific prior 281.1Srin * written permission. 291.1Srin * 301.1Srin * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 311.1Srin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 321.1Srin * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 331.1Srin * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 341.1Srin * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 351.1Srin * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 361.1Srin * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 371.1Srin * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 381.1Srin * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 391.1Srin * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 401.1Srin * POSSIBILITY OF SUCH DAMAGE. 411.1Srin */ 421.1Srin 431.1Srin/* 441.1Srin * Copyright (C) 1995, 1996 Wolfgang Solfrank. 451.1Srin * Copyright (C) 1995, 1996 TooLs GmbH. 461.1Srin * All rights reserved. 471.1Srin * 481.1Srin * Redistribution and use in source and binary forms, with or without 491.1Srin * modification, are permitted provided that the following conditions 501.1Srin * are met: 511.1Srin * 1. Redistributions of source code must retain the above copyright 521.1Srin * notice, this list of conditions and the following disclaimer. 531.1Srin * 2. Redistributions in binary form must reproduce the above copyright 541.1Srin * notice, this list of conditions and the following disclaimer in the 551.1Srin * documentation and/or other materials provided with the distribution. 561.1Srin * 3. All advertising materials mentioning features or use of this software 571.1Srin * must display the following acknowledgement: 581.1Srin * This product includes software developed by TooLs GmbH. 591.1Srin * 4. The name of TooLs GmbH may not be used to endorse or promote products 601.1Srin * derived from this software without specific prior written permission. 611.1Srin * 621.1Srin * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 631.1Srin * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 641.1Srin * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 651.1Srin * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 661.1Srin * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 671.1Srin * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 681.1Srin * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 691.1Srin * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 701.1Srin * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 711.1Srin * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 721.1Srin */ 731.1Srin 741.1Srin#include <sys/cdefs.h> 751.3Sandvar__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.3 2021/09/19 11:37:00 andvar Exp $"); 761.1Srin 771.1Srin#include "opt_ddb.h" 781.1Srin#include "opt_pci.h" 791.1Srin 801.1Srin#include <sys/param.h> 811.1Srin#include <sys/bus.h> 821.1Srin#include <sys/device.h> 831.1Srin#include <sys/kernel.h> 841.1Srin#include <sys/module.h> 851.1Srin#include <sys/reboot.h> 861.1Srin#include <sys/systm.h> 871.1Srin 881.1Srin#include <machine/dht.h> 891.1Srin 901.1Srin#include <powerpc/spr.h> 911.1Srin#include <powerpc/ibm4xx/spr.h> 921.1Srin 931.1Srin#include <powerpc/ibm4xx/cpu.h> 941.1Srin#include <powerpc/ibm4xx/dcr4xx.h> 951.1Srin#include <powerpc/ibm4xx/ibm405gp.h> 961.1Srin#include <powerpc/ibm4xx/openbios.h> 971.1Srin#include <powerpc/ibm4xx/tlb.h> 981.1Srin 991.1Srin#include "com.h" 1001.1Srin#if NCOM > 0 1011.1Srin#include <sys/termios.h> 1021.1Srin#include <dev/ic/comreg.h> 1031.1Srin#include <dev/ic/comvar.h> 1041.1Srin#include <powerpc/ibm4xx/dev/comopbvar.h> 1051.1Srin#ifndef CONADDR 1061.1Srin#define CONADDR IBM405GP_UART0_BASE 1071.1Srin#endif 1081.1Srin#ifndef CONSPEED 1091.1Srin#define CONSPEED B115200 1101.1Srin#endif 1111.1Srin#ifndef CONMODE 1121.1Srin#define CONMODE TTYDEF_CFLAG 1131.1Srin#endif 1141.1Srin#endif /* NCOM > 0 */ 1151.1Srin 1161.1Srin#include "emac.h" 1171.1Srin#if NEMAC > 0 1181.1Srin#include <net/if_ether.h> 1191.1Srin#endif 1201.1Srin 1211.1Srin#include "pci.h" 1221.1Srin#if NPCI > 0 1231.1Srin#ifndef PCI_NETBSD_CONFIGURE 1241.1Srin#error options PCI_NETBSD_CONFIGURE is mandatory. 1251.1Srin#endif 1261.1Srin#include <powerpc/ibm4xx/pci_machdep.h> 1271.1Srin#include <dev/pci/pciconf.h> 1281.1Srin#include <dev/pci/pcivar.h> 1291.1Srin#endif 1301.1Srin 1311.1Srin#define TLB_PG_SIZE (16 * 1024 * 1024) 1321.1Srin 1331.1Srinstatic u_int memsize; 1341.1Srin 1351.1Srinvoid initppc(vaddr_t, vaddr_t, char *, void *); 1361.1Srin 1371.1Srin/* 1381.1Srin * Get memory size from SDRAM bank register. 1391.1Srin */ 1401.1Srinstatic u_int 1411.1Srindht_memsize(void) 1421.1Srin{ 1431.1Srin u_int total = 0; 1441.1Srin uint32_t val, addr; 1451.1Srin 1461.1Srin for (addr = DCR_SDRAM0_B0CR; addr <= DCR_SDRAM0_B3CR; addr += 4) { 1471.1Srin mtdcr(DCR_SDRAM0_CFGADDR, addr); 1481.1Srin val = mfdcr(DCR_SDRAM0_CFGDATA); 1491.1Srin if (val & SDRAM0_BnCR_EN) 1501.1Srin total += SDRAM0_BnCR_SZ(val); 1511.1Srin } 1521.1Srin return total; 1531.1Srin} 1541.1Srin 1551.1Srinvoid 1561.1Srinconsinit(void) 1571.1Srin{ 1581.1Srin 1591.1Srin#if NCOM > 0 1601.1Srin com_opb_cnattach(DHT_COM_FREQ, CONADDR, CONSPEED, CONMODE); 1611.1Srin#endif 1621.1Srin} 1631.1Srin 1641.1Srinvoid 1651.1Srininitppc(vaddr_t startkernel, vaddr_t endkernel, char *args, void *info_block) 1661.1Srin{ 1671.1Srin 1681.1Srin /* Disable all external interrupts */ 1691.1Srin mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, 0); 1701.1Srin 1711.1Srin memsize = dht_memsize(); 1721.1Srin 1731.1Srin /* Linear map kernel memory */ 1741.1Srin for (vaddr_t va = 0; va < endkernel; va += TLB_PG_SIZE) 1751.1Srin ppc4xx_tlb_reserve(va, va, TLB_PG_SIZE, TLB_EX); 1761.1Srin 1771.1Srin /* Map console after physmem (see pmap_tlbmiss()) */ 1781.1Srin ppc4xx_tlb_reserve(IBM405GP_UART0_BASE, roundup(memsize, TLB_PG_SIZE), 1791.1Srin TLB_PG_SIZE, TLB_I | TLB_G); 1801.1Srin 1811.1Srin /* Disable all timers */ 1821.1Srin mtspr(SPR_TCR, 0); 1831.1Srin 1841.1Srin ibm40x_memsize_init(memsize, startkernel); 1851.1Srin ibm4xx_init(startkernel, endkernel, pic_ext_intr); 1861.1Srin 1871.1Srin#ifdef DDB 1881.1Srin if (boothowto & RB_KDB) 1891.1Srin Debugger(); 1901.1Srin#endif 1911.1Srin} 1921.1Srin 1931.1Srinvoid 1941.1Srincpu_startup(void) 1951.1Srin{ 1961.1Srin prop_number_t pn; 1971.1Srin 1981.1Srin ibm4xx_cpu_startup("DHT Walnut 405GP Evaluation Board"); 1991.1Srin 2001.1Srin /* 2011.1Srin * Set up the board properties database. 2021.1Srin */ 2031.1Srin board_info_init(); 2041.1Srin 2051.1Srin pn = prop_number_create_integer(DHT_CPU_FREQ); 2061.1Srin KASSERT(pn != NULL); 2071.1Srin if (prop_dictionary_set(board_properties, "processor-frequency", pn) == 2081.1Srin false) 2091.1Srin panic("setting processor-frequency"); 2101.1Srin prop_object_release(pn); 2111.1Srin 2121.1Srin pn = prop_number_create_integer(memsize); 2131.1Srin KASSERT(pn != NULL); 2141.1Srin if (prop_dictionary_set(board_properties, "mem-size", pn) == false) 2151.1Srin panic("setting mem-size"); 2161.1Srin prop_object_release(pn); 2171.1Srin 2181.1Srin#if NEMAC > 0 2191.1Srin /* 2201.1Srin * XXX 2211.1Srin * Unfortunately, no MAC address is assigned to this board. 2221.1Srin * Set fake address de:ad:be:ef:00:00. 2231.1Srin * 2241.1Srin * XXX 2251.1Srin * This should be same with what U-Boot/PPC-Boot set. 2261.1Srin */ 2271.1Srin static uint8_t enaddr[ETHER_ADDR_LEN]; 2281.1Srin enaddr[0] = 0xde; enaddr[1] = 0xad; enaddr[2] = 0xbe; 2291.1Srin enaddr[3] = 0xef; enaddr[4] = 0x00; enaddr[5] = 0x00; 2301.1Srin prop_data_t pd = prop_data_create_data_nocopy(enaddr, ETHER_ADDR_LEN); 2311.1Srin KASSERT(pd != NULL); 2321.1Srin if (prop_dictionary_set(board_properties, "emac0-mac-addr", pd) == 2331.1Srin false) 2341.1Srin panic("setting emac0-mac-addr"); 2351.1Srin prop_object_release(pd); 2361.1Srin#endif 2371.1Srin 2381.1Srin /* 2391.1Srin * Now that we have VM, malloc()s are OK in bus_space. 2401.1Srin */ 2411.1Srin bus_space_mallocok(); 2421.1Srin 2431.1Srin /* 2441.1Srin * No fake mapiodev. 2451.1Srin */ 2461.1Srin fake_mapiodev = 0; 2471.1Srin} 2481.1Srin 2491.1Srin#if NPCI > 0 2501.1Srinint 2511.1Srinibm4xx_pci_bus_maxdevs(void *v, int busno) 2521.1Srin{ 2531.1Srin 2541.1Srin return 32; 2551.1Srin} 2561.1Srin 2571.1Srin/* 2581.1Srin * This is only possible mapping known to work b/w PCI devices and IRQ pins. 2591.1Srin */ 2601.1Srin#define DEV_TO_IRQ(dev) (27 + (dev)) 2611.1Srin#define PARENT_DEV(swiz, dev) ((swiz) - (dev)) 2621.1Srin 2631.1Srinint 2641.1Srinibm4xx_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 2651.1Srin{ 2661.1Srin int pin = pa->pa_intrpin, bus = pa->pa_bus, dev = pa->pa_device; 2671.1Srin 2681.1Srin if (pin <= 0 || pin > 4) 2691.1Srin goto bad; 2701.1Srin 2711.1Srin if (bus != 0) { 2721.1Srin /* 2731.1Srin * XXX 2741.1Srin * We only support ppb(4) directly attached to pci0. 2751.1Srin */ 2761.1Srin dev = PARENT_DEV(pa->pa_intrswiz, dev); 2771.1Srin goto out; 2781.1Srin } 2791.1Srin 2801.1Srin switch (dev) { 2811.1Srin case 2: 2821.1Srin case 3: 2831.1Srin case 4: 2841.1Srinout: 2851.1Srin *ihp = DEV_TO_IRQ(dev); 2861.1Srin return 0; 2871.1Srin default: 2881.1Srinbad: 2891.1Srin printf("%s: invalid request: bus %d dev %d pin %d\n", 2901.1Srin __func__, bus, dev, pin); 2911.1Srin *ihp = -1; 2921.1Srin return 1; 2931.1Srin } 2941.1Srin} 2951.1Srin 2961.1Srinvoid 2971.1Srinibm4xx_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, 2981.1Srin int *iline) 2991.1Srin{ 3001.1Srin 3011.1Srin if (bus != 0) { 3021.1Srin /* 3031.1Srin * XXX 3041.3Sandvar * See comment above. 3051.1Srin */ 3061.1Srin dev = PARENT_DEV(swiz, dev); 3071.1Srin goto out; 3081.1Srin } 3091.1Srin 3101.1Srin switch (dev) { 3111.1Srin case 2: 3121.1Srin case 3: 3131.1Srin case 4: 3141.1Srinout: 3151.1Srin *iline = DEV_TO_IRQ(dev); 3161.1Srin break; 3171.1Srin default: 3181.1Srin printf("%s: invalid request: bus %d dev %d pin %d swiz %d\n", 3191.1Srin __func__, bus, dev, pin, swiz); 3201.1Srin *iline = 0; 3211.1Srin break; 3221.1Srin } 3231.1Srin} 3241.1Srin#endif /* NPCI > 0 */ 325