machdep.c revision 1.61 
1/*	$NetBSD: machdep.c,v 1.61 2008/11/11 06:46:42 dyoung Exp $	*/
2
3/*-
4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9 * Simulation Facility, NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*-
34 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
35 * All rights reserved.
36 *
37 * This code is derived from software contributed to Berkeley by
38 * William Jolitz.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 * 1. Redistributions of source code must retain the above copyright
44 *    notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 *    notice, this list of conditions and the following disclaimer in the
47 *    documentation and/or other materials provided with the distribution.
48 * 3. Neither the name of the University nor the names of its contributors
49 *    may be used to endorse or promote products derived from this software
50 *    without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
55 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
62 * SUCH DAMAGE.
63 *
64 *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
65 */
66
67#include <sys/cdefs.h>
68__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.61 2008/11/11 06:46:42 dyoung Exp $");
69
70#include "opt_ddb.h"
71#include "opt_kgdb.h"
72#include "opt_memsize.h"
73#include "opt_initbsc.h"
74
75#include <sys/param.h>
76#include <sys/systm.h>
77#include <sys/kernel.h>
78#include <sys/user.h>
79#include <sys/mount.h>
80#include <sys/reboot.h>
81#include <sys/sysctl.h>
82#include <sys/ksyms.h>
83#include <sys/device.h>
84
85#include <uvm/uvm_extern.h>
86
87#include <dev/cons.h>
88
89#include <sh3/bscreg.h>
90#include <sh3/cpgreg.h>
91#include <sh3/cache_sh3.h>
92#include <sh3/cache_sh4.h>
93#include <sh3/exception.h>
94
95#include <machine/bus.h>
96#include <machine/intr.h>
97
98#ifdef DDB
99#include <machine/db_machdep.h>
100#include <ddb/db_extern.h>
101#endif
102
103#include "ksyms.h"
104
105/* the following is used externally (sysctl_hw) */
106char machine[] = MACHINE;		/* evbsh3 */
107char machine_arch[] = MACHINE_ARCH;	/* sh3eb or sh3el */
108
109void initSH3 __P((void *));
110void LoadAndReset __P((const char *));
111void XLoadAndReset __P((char *));
112
113/*
114 * Machine-dependent startup code
115 *
116 * This is called from main() in kern/main.c.
117 */
118void
119cpu_startup()
120{
121
122	sh_startup();
123}
124
125/*
126 * machine dependent system variables.
127 */
128static int
129sysctl_machdep_loadandreset(SYSCTLFN_ARGS)
130{
131	const char *osimage;
132	int error;
133
134	error = sysctl_lookup(SYSCTLFN_CALL(__UNCONST(rnode)));
135	if (error || newp == NULL)
136		return (error);
137
138	osimage = (const char *)(*(const u_long *)newp);
139	LoadAndReset(osimage);
140	/* not reach here */
141	return (0);
142}
143
144SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup")
145{
146
147	sysctl_createv(clog, 0, NULL, NULL,
148		       CTLFLAG_PERMANENT,
149		       CTLTYPE_NODE, "machdep", NULL,
150		       NULL, 0, NULL, 0,
151		       CTL_MACHDEP, CTL_EOL);
152
153	sysctl_createv(clog, 0, NULL, NULL,
154		       CTLFLAG_PERMANENT,
155		       CTLTYPE_STRUCT, "console_device", NULL,
156		       sysctl_consdev, 0, NULL, sizeof(dev_t),
157		       CTL_MACHDEP, CPU_CONSDEV, CTL_EOL);
158/*
159<atatat> okay...your turn to play.
160<atatat> pick a number.
161<kjk> 98752.
162*/
163	sysctl_createv(clog, 0, NULL, NULL,
164		       CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE,
165		       CTLTYPE_INT, "load_and_reset", NULL,
166		       sysctl_machdep_loadandreset, 98752, NULL, 0,
167		       CTL_MACHDEP, CPU_LOADANDRESET, CTL_EOL);
168}
169
170void
171cpu_reboot(howto, bootstr)
172	int howto;
173	char *bootstr;
174{
175	static int waittime = -1;
176
177	if (cold) {
178		howto |= RB_HALT;
179		goto haltsys;
180	}
181
182	boothowto = howto;
183	if ((howto & RB_NOSYNC) == 0 && waittime < 0) {
184		waittime = 0;
185		vfs_shutdown();
186		/*
187		 * If we've been adjusting the clock, the todr
188		 * will be out of synch; adjust it now.
189		 */
190		/* resettodr(); */
191	}
192
193	/* Disable interrupts. */
194	splhigh();
195
196	/* Do a dump if requested. */
197	if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
198		dumpsys();
199
200haltsys:
201	doshutdownhooks();
202
203	pmf_system_shutdown(boothowto);
204
205	if (howto & RB_HALT) {
206		printf("\n");
207		printf("The operating system has halted.\n");
208		printf("Please press any key to reboot.\n\n");
209		cngetc();
210	}
211
212	printf("rebooting...\n");
213	cpu_reset();
214	for(;;)
215		;
216	/*NOTREACHED*/
217}
218
219void
220initSH3(void *pc)	/* XXX return address */
221{
222	extern char edata[], end[];
223	vaddr_t kernend;
224
225	/* Clear bss */
226	memset(edata, 0, end - edata);
227
228	/* Initilize CPU ops. */
229#if defined(SH3) && defined(SH4)
230#error "don't define both SH3 and SH4"
231#elif defined(SH3)
232#if defined(SH7708)
233	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708);
234#elif defined(SH7708S)
235	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708S);
236#elif defined(SH7708R)
237	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708R);
238#elif defined(SH7709)
239	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709);
240#elif defined(SH7709A)
241	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A);
242#else
243#error "unsupported SH3 variants"
244#endif
245#elif defined(SH4)
246#if defined(SH7750)
247	sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750);
248#elif defined(SH7750S)
249	sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750S);
250#else
251#error "unsupported SH4 variants"
252#endif
253#else
254#error "define SH3 or SH4"
255#endif
256	/* Console */
257	consinit();
258
259	/* Load memory to UVM */
260	kernend = atop(round_page(SH3_P1SEG_TO_PHYS(end)));
261	physmem = atop(IOM_RAM_SIZE);
262	uvm_page_physload(
263		kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE),
264		kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE),
265		VM_FREELIST_DEFAULT);
266
267	/* Initialize proc0 u-area */
268	sh_proc0_init();
269
270	/* Initialize pmap and start to address translation */
271	pmap_bootstrap();
272
273#if NKSYMS || defined(DDB) || defined(LKM)
274	ksyms_init(0, NULL, NULL);
275#endif
276
277	/*
278	 * XXX We can't return here, because we change stack pointer.
279	 *     So jump to return address directly.
280	 */
281	__asm volatile (
282		"jmp	@%0;"
283		"mov	%1, r15"
284		:: "r"(pc),"r"(lwp0.l_md.md_pcb->pcb_sf.sf_r7_bank));
285}
286
287/*
288 * consinit:
289 * initialize the system console.
290 * XXX - shouldn't deal with this initted thing, but then,
291 * it shouldn't be called from init386 either.
292 */
293void
294consinit()
295{
296	static int initted;
297
298	if (initted)
299		return;
300	initted = 1;
301
302	cninit();
303}
304
305int
306bus_space_map (t, addr, size, flags, bshp)
307	bus_space_tag_t t;
308	bus_addr_t addr;
309	bus_size_t size;
310	int flags;
311	bus_space_handle_t *bshp;
312{
313
314	*bshp = (bus_space_handle_t)addr;
315
316	return 0;
317}
318
319int
320sh_memio_subregion(t, bsh, offset, size, nbshp)
321	bus_space_tag_t t;
322	bus_space_handle_t bsh;
323	bus_size_t offset, size;
324	bus_space_handle_t *nbshp;
325{
326
327	*nbshp = bsh + offset;
328	return (0);
329}
330
331int
332sh_memio_alloc(t, rstart, rend, size, alignment, boundary, flags,
333	       bpap, bshp)
334	bus_space_tag_t t;
335	bus_addr_t rstart, rend;
336	bus_size_t size, alignment, boundary;
337	int flags;
338	bus_addr_t *bpap;
339	bus_space_handle_t *bshp;
340{
341	*bshp = *bpap = rstart;
342
343	return (0);
344}
345
346void
347sh_memio_free(t, bsh, size)
348	bus_space_tag_t t;
349	bus_space_handle_t bsh;
350	bus_size_t size;
351{
352
353}
354
355void
356sh_memio_unmap(t, bsh, size)
357	bus_space_tag_t t;
358	bus_space_handle_t bsh;
359	bus_size_t size;
360{
361	return;
362}
363
364#ifdef SH4_PCMCIA
365
366int
367shpcmcia_memio_map(t, bpa, size, flags, bshp)
368	bus_space_tag_t t;
369	bus_addr_t bpa;
370	bus_size_t size;
371	int flags;
372	bus_space_handle_t *bshp;
373{
374	int error;
375	struct extent *ex;
376	bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT;
377
378	if (pt != SH3_BUS_SPACE_PCMCIA_IO &&
379	    pt != SH3_BUS_SPACE_PCMCIA_MEM &&
380	    pt != SH3_BUS_SPACE_PCMCIA_ATT) {
381		*bshp = (bus_space_handle_t)bpa;
382
383		return 0;
384	}
385
386	ex = iomem_ex;
387
388#if 0
389	/*
390	 * Before we go any further, let's make sure that this
391	 * region is available.
392	 */
393	error = extent_alloc_region(ex, bpa, size,
394				    EX_NOWAIT | EX_MALLOCOK );
395	if (error){
396		printf("sh3_pcmcia_memio_map:extent_alloc_region error\n");
397		return (error);
398	}
399#endif
400
401	/*
402	 * For memory space, map the bus physical address to
403	 * a kernel virtual address.
404	 */
405	error = shpcmcia_mem_add_mapping(bpa, size, (int)t, bshp );
406#if 0
407	if (error) {
408		if (extent_free(ex, bpa, size, EX_NOWAIT | EX_MALLOCOK )) {
409			printf("sh3_pcmcia_memio_map: pa 0x%lx, size 0x%lx\n",
410			       bpa, size);
411			printf("sh3_pcmcia_memio_map: can't free region\n");
412		}
413	}
414#endif
415
416	return (error);
417}
418
419int
420shpcmcia_mem_add_mapping(bpa, size, type, bshp)
421	bus_addr_t bpa;
422	bus_size_t size;
423	int type;
424	bus_space_handle_t *bshp;
425{
426	u_long pa, endpa;
427	vaddr_t va;
428	pt_entry_t *pte;
429	unsigned int m = 0;
430	int io_type = type & ~SH3_BUS_SPACE_PCMCIA_8BIT;
431
432	pa = sh3_trunc_page(bpa);
433	endpa = sh3_round_page(bpa + size);
434
435#ifdef DIAGNOSTIC
436	if (endpa <= pa)
437		panic("sh3_pcmcia_mem_add_mapping: overflow");
438#endif
439
440	va = uvm_km_alloc(kernel_map, endpa - pa, 0,
441	    UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
442	if (va == 0){
443		printf("shpcmcia_add_mapping: nomem \n");
444		return (ENOMEM);
445	}
446
447	*bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
448
449#define MODE(t, s)							\
450	(t) & SH3_BUS_SPACE_PCMCIA_8BIT ?				\
451		_PG_PCMCIA_ ## s ## 8 :					\
452		_PG_PCMCIA_ ## s ## 16
453	switch (io_type) {
454	default:
455		panic("unknown pcmcia space.");
456		/* NOTREACHED */
457	case SH3_BUS_SPACE_PCMCIA_IO:
458		m = MODE(type, IO);
459		break;
460	case SH3_BUS_SPACE_PCMCIA_MEM:
461		m = MODE(type, MEM);
462		break;
463	case SH3_BUS_SPACE_PCMCIA_ATT:
464		m = MODE(type, ATTR);
465		break;
466	}
467#undef MODE
468
469	for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
470		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
471		pte = __pmap_kpte_lookup(va);
472		KDASSERT(pte);
473		*pte |= m;  /* PTEA PCMCIA assistant bit */
474		sh_tlb_update(0, va, *pte);
475	}
476
477	return 0;
478}
479
480void
481shpcmcia_memio_unmap(t, bsh, size)
482	bus_space_tag_t t;
483	bus_space_handle_t bsh;
484	bus_size_t size;
485{
486	struct extent *ex;
487	u_long va, endva;
488	bus_addr_t bpa;
489	bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT;
490
491	if (pt != SH3_BUS_SPACE_PCMCIA_IO &&
492	    pt != SH3_BUS_SPACE_PCMCIA_MEM &&
493	    pt != SH3_BUS_SPACE_PCMCIA_ATT) {
494		return ;
495	}
496
497	ex = iomem_ex;
498
499	va = sh3_trunc_page(bsh);
500	endva = sh3_round_page(bsh + size);
501
502#ifdef DIAGNOSTIC
503	if (endva <= va)
504		panic("sh3_pcmcia_memio_unmap: overflow");
505#endif
506
507	pmap_extract(pmap_kernel(), va, &bpa);
508	bpa += bsh & PGOFSET;
509
510	/*
511	 * Free the kernel virtual mapping.
512	 */
513	pmap_kremove(va, endva - va);
514	pmap_update(pmap_kernel());
515	uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY);
516
517#if 0
518	if (extent_free(ex, bpa, size,
519			EX_NOWAIT | EX_MALLOCOK)) {
520		printf("sh3_pcmcia_memio_unmap: %s 0x%lx, size 0x%lx\n",
521		       "pa", bpa, size);
522		printf("sh3_pcmcia_memio_unmap: can't free region\n");
523	}
524#endif
525}
526
527void
528shpcmcia_memio_free(t, bsh, size)
529	bus_space_tag_t t;
530	bus_space_handle_t bsh;
531	bus_size_t size;
532{
533
534	/* sh3_pcmcia_memio_unmap() does all that we need to do. */
535	shpcmcia_memio_unmap(t, bsh, size);
536}
537
538int
539shpcmcia_memio_subregion(t, bsh, offset, size, nbshp)
540	bus_space_tag_t t;
541	bus_space_handle_t bsh;
542	bus_size_t offset, size;
543	bus_space_handle_t *nbshp;
544{
545
546	*nbshp = bsh + offset;
547	return (0);
548}
549
550#endif /* SH4_PCMCIA */
551
552#if !defined(DONT_INIT_BSC)
553/*
554 * InitializeBsc
555 * : BSC(Bus State Controller)
556 */
557void InitializeBsc __P((void));
558
559void
560InitializeBsc()
561{
562
563	/*
564	 * Drive RAS,CAS in stand by mode and bus release mode
565	 * Area0 = Normal memory, Area5,6=Normal(no burst)
566	 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory
567	 * Area4 = Normal Memory
568	 * Area6 = Normal memory
569	 */
570#if defined(SH3)
571	_reg_write_2(SH3_BCR1, BSC_BCR1_VAL);
572#elif defined(SH4)
573	_reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
574#endif
575
576	/*
577	 * Bus Width
578	 * Area4: Bus width = 16bit
579	 * Area6,5 = 16bit
580	 * Area1 = 8bit
581	 * Area2,3: Bus width = 32bit
582	 */
583	_reg_write_2(SH_(BCR2), BSC_BCR2_VAL);
584
585	/*
586	 * Idle cycle number in transition area and read to write
587	 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3
588	 * Area1 = 3, Area0 = 3
589	 */
590#if defined(SH3)
591	_reg_write_2(SH3_WCR1, BSC_WCR1_VAL);
592#elif defined(SH4)
593	_reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
594#endif
595
596	/*
597	 * Wait cycle
598	 * Area 6 = 6
599	 * Area 5 = 2
600	 * Area 4 = 10
601	 * Area 3 = 3
602	 * Area 2,1 = 3
603	 * Area 0 = 6
604	 */
605#if defined(SH3)
606	_reg_write_2(SH3_WCR2, BSC_WCR2_VAL);
607#elif defined(SH4)
608	_reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
609#endif
610
611#if defined(SH4) && defined(BSC_WCR3_VAL)
612	_reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
613#endif
614
615	/*
616	 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle,
617	 * write pre-charge=1cycle
618	 * CAS before RAS refresh RAS assert time = 3 cycle
619	 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON
620	 * CAS before RAS refresh ON, EDO DRAM
621	 */
622#if defined(SH3)
623	_reg_write_2(SH3_MCR, BSC_MCR_VAL);
624#elif defined(SH4)
625	_reg_write_4(SH4_MCR, BSC_MCR_VAL);
626#endif
627
628#if defined(BSC_SDMR2_VAL)
629	_reg_write_1(BSC_SDMR2_VAL, 0);
630#endif
631
632#if defined(BSC_SDMR3_VAL)
633#if !(defined(COMPUTEXEVB) && defined(SH7709A))
634	_reg_write_1(BSC_SDMR3_VAL, 0);
635#else
636	_reg_write_2(0x1a000000, 0);	/* ADDSET */
637	_reg_write_1(BSC_SDMR3_VAL, 0);
638	_reg_write_2(0x18000000, 0);	/* ADDRST */
639#endif /* !(COMPUTEXEVB && SH7709A) */
640#endif /* BSC_SDMR3_VAL */
641
642	/*
643	 * PCMCIA Control Register
644	 * OE/WE assert delay 3.5 cycle
645	 * OE/WE negate-address delay 3.5 cycle
646	 */
647#ifdef BSC_PCR_VAL
648	_reg_write_2(SH_(PCR), BSC_PCR_VAL);
649#endif
650
651	/*
652	 * Refresh Timer Control/Status Register
653	 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt
654	 * Count Limit = 1024
655	 * In following statement, the reason why high byte = 0xa5(a4 in RFCR)
656	 * is the rule of SH3 in writing these register.
657	 */
658	_reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL);
659
660	/*
661	 * Refresh Timer Counter
662	 * Initialize to 0
663	 */
664#ifdef BSC_RTCNT_VAL
665	_reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL);
666#endif
667
668	/* set Refresh Time Constant Register */
669	_reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL);
670
671	/* init Refresh Count Register */
672#ifdef BSC_RFCR_VAL
673	_reg_write_2(SH_(RFCR), BSC_RFCR_VAL);
674#endif
675
676	/*
677	 * Clock Pulse Generator
678	 */
679	/* Set Clock mode (make internal clock double speed) */
680	_reg_write_2(SH_(FRQCR), FRQCR_VAL);
681
682	/*
683	 * Cache
684	 */
685#ifndef CACHE_DISABLE
686	/* Cache ON */
687	_reg_write_4(SH_(CCR), 0x1);
688#endif
689}
690#endif /* !DONT_INIT_BSC */
691
692
693 /* XXX This value depends on physical available memory */
694#define OSIMAGE_BUF_ADDR	(IOM_RAM_BEGIN + 0x00400000)
695
696void
697LoadAndReset(osimage)
698	const char *osimage;
699{
700	void *buf_addr;
701	u_long size;
702	const u_long *src;
703	u_long *dest;
704	u_long csum = 0;
705	u_long csum2 = 0;
706	u_long size2;
707
708	printf("LoadAndReset: copy start\n");
709	buf_addr = (void *)OSIMAGE_BUF_ADDR;
710
711	size = *(const u_long *)osimage;
712	src = (const u_long *)osimage;
713	dest = buf_addr;
714
715	size = (size + sizeof(u_long) * 2 + 3) >> 2;
716	size2 = size;
717
718	while (size--) {
719		csum += *src;
720		*dest++ = *src++;
721	}
722
723	dest = buf_addr;
724	while (size2--)
725		csum2 += *dest++;
726
727	printf("LoadAndReset: copy end[%lx,%lx]\n", csum, csum2);
728	printf("start XLoadAndReset\n");
729
730	/* mask all externel interrupt (XXX) */
731
732	XLoadAndReset(buf_addr);
733}
734
735void
736intc_intr(int ssr, int spc, int ssp)
737{
738	struct intc_intrhand *ih;
739	struct clockframe cf;
740	int s, evtcode;
741
742	switch (cpu_product) {
743	case CPU_PRODUCT_7708:
744	case CPU_PRODUCT_7708S:
745	case CPU_PRODUCT_7708R:
746		evtcode = _reg_read_4(SH3_INTEVT);
747		break;
748	case CPU_PRODUCT_7709:
749	case CPU_PRODUCT_7709A:
750		evtcode = _reg_read_4(SH7709_INTEVT2);
751		break;
752	case CPU_PRODUCT_7750:
753	case CPU_PRODUCT_7750S:
754		evtcode = _reg_read_4(SH4_INTEVT);
755		break;
756	default:
757#ifdef DIAGNOSTIC
758		panic("intr_intc: cpu_product %d unhandled!", cpu_product);
759#endif
760		return;
761	}
762
763	ih = EVTCODE_IH(evtcode);
764	KDASSERT(ih->ih_func);
765	/*
766	 * On entry, all interrrupts are disabled,
767	 * and exception is enabled for P3 access. (kernel stack is P3,
768	 * SH3 may or may not cause TLB miss when access stack.)
769	 * Enable higher level interrupt here.
770	 */
771	s = _cpu_intr_resume(ih->ih_level);
772
773	switch (evtcode) {
774	default:
775		(*ih->ih_func)(ih->ih_arg);
776		break;
777	case SH_INTEVT_TMU0_TUNI0:
778		cf.spc = spc;
779		cf.ssr = ssr;
780		cf.ssp = ssp;
781		(*ih->ih_func)(&cf);
782		break;
783	case SH_INTEVT_NMI:
784		printf("NMI ignored.\n");
785		break;
786	}
787}
788
789