machdep.c revision 1.65 
1/*	$NetBSD: machdep.c,v 1.65 2009/03/14 15:36:06 dsl Exp $	*/
2
3/*-
4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9 * Simulation Facility, NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*-
34 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
35 * All rights reserved.
36 *
37 * This code is derived from software contributed to Berkeley by
38 * William Jolitz.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 * 1. Redistributions of source code must retain the above copyright
44 *    notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 *    notice, this list of conditions and the following disclaimer in the
47 *    documentation and/or other materials provided with the distribution.
48 * 3. Neither the name of the University nor the names of its contributors
49 *    may be used to endorse or promote products derived from this software
50 *    without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
55 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
62 * SUCH DAMAGE.
63 *
64 *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
65 */
66
67#include <sys/cdefs.h>
68__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.65 2009/03/14 15:36:06 dsl Exp $");
69
70#include "opt_ddb.h"
71#include "opt_kgdb.h"
72#include "opt_memsize.h"
73#include "opt_initbsc.h"
74
75#include <sys/param.h>
76#include <sys/systm.h>
77#include <sys/kernel.h>
78#include <sys/user.h>
79#include <sys/mount.h>
80#include <sys/reboot.h>
81#include <sys/sysctl.h>
82#include <sys/ksyms.h>
83#include <sys/device.h>
84
85#include <uvm/uvm_extern.h>
86
87#include <dev/cons.h>
88
89#include <sh3/bscreg.h>
90#include <sh3/cpgreg.h>
91#include <sh3/cache_sh3.h>
92#include <sh3/cache_sh4.h>
93#include <sh3/exception.h>
94
95#include <machine/bus.h>
96#include <machine/intr.h>
97
98#ifdef DDB
99#include <machine/db_machdep.h>
100#include <ddb/db_extern.h>
101#endif
102
103#include "ksyms.h"
104
105/* the following is used externally (sysctl_hw) */
106char machine[] = MACHINE;		/* evbsh3 */
107char machine_arch[] = MACHINE_ARCH;	/* sh3eb or sh3el */
108
109void initSH3(void *);
110void LoadAndReset(const char *);
111void XLoadAndReset(char *);
112
113/*
114 * Machine-dependent startup code
115 *
116 * This is called from main() in kern/main.c.
117 */
118void
119cpu_startup()
120{
121
122	sh_startup();
123}
124
125/*
126 * machine dependent system variables.
127 */
128static int
129sysctl_machdep_loadandreset(SYSCTLFN_ARGS)
130{
131	const char *osimage;
132	int error;
133
134	error = sysctl_lookup(SYSCTLFN_CALL(__UNCONST(rnode)));
135	if (error || newp == NULL)
136		return (error);
137
138	osimage = (const char *)(*(const u_long *)newp);
139	LoadAndReset(osimage);
140	/* not reach here */
141	return (0);
142}
143
144SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup")
145{
146
147	sysctl_createv(clog, 0, NULL, NULL,
148		       CTLFLAG_PERMANENT,
149		       CTLTYPE_NODE, "machdep", NULL,
150		       NULL, 0, NULL, 0,
151		       CTL_MACHDEP, CTL_EOL);
152
153	sysctl_createv(clog, 0, NULL, NULL,
154		       CTLFLAG_PERMANENT,
155		       CTLTYPE_STRUCT, "console_device", NULL,
156		       sysctl_consdev, 0, NULL, sizeof(dev_t),
157		       CTL_MACHDEP, CPU_CONSDEV, CTL_EOL);
158/*
159<atatat> okay...your turn to play.
160<atatat> pick a number.
161<kjk> 98752.
162*/
163	sysctl_createv(clog, 0, NULL, NULL,
164		       CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE,
165		       CTLTYPE_INT, "load_and_reset", NULL,
166		       sysctl_machdep_loadandreset, 98752, NULL, 0,
167		       CTL_MACHDEP, CPU_LOADANDRESET, CTL_EOL);
168}
169
170void
171cpu_reboot(int howto, char *bootstr)
172{
173	static int waittime = -1;
174
175	if (cold) {
176		howto |= RB_HALT;
177		goto haltsys;
178	}
179
180	boothowto = howto;
181	if ((howto & RB_NOSYNC) == 0 && waittime < 0) {
182		waittime = 0;
183		vfs_shutdown();
184		/*
185		 * If we've been adjusting the clock, the todr
186		 * will be out of synch; adjust it now.
187		 */
188		/* resettodr(); */
189	}
190
191	/* Disable interrupts. */
192	splhigh();
193
194	/* Do a dump if requested. */
195	if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
196		dumpsys();
197
198haltsys:
199	doshutdownhooks();
200
201	pmf_system_shutdown(boothowto);
202
203	if (howto & RB_HALT) {
204		printf("\n");
205		printf("The operating system has halted.\n");
206		printf("Please press any key to reboot.\n\n");
207		cngetc();
208	}
209
210	printf("rebooting...\n");
211	cpu_reset();
212	for(;;)
213		;
214	/*NOTREACHED*/
215}
216
217void
218initSH3(void *pc)	/* XXX return address */
219{
220	extern char edata[], end[];
221	vaddr_t kernend;
222
223	/* Clear bss */
224	memset(edata, 0, end - edata);
225
226	/* Initilize CPU ops. */
227#if defined(SH3) && defined(SH4)
228#error "don't define both SH3 and SH4"
229#elif defined(SH3)
230#if defined(SH7708)
231	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708);
232#elif defined(SH7708S)
233	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708S);
234#elif defined(SH7708R)
235	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708R);
236#elif defined(SH7709)
237	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709);
238#elif defined(SH7709A)
239	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A);
240#else
241#error "unsupported SH3 variants"
242#endif
243#elif defined(SH4)
244#if defined(SH7750)
245	sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750);
246#elif defined(SH7750S)
247	sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750S);
248#else
249#error "unsupported SH4 variants"
250#endif
251#else
252#error "define SH3 or SH4"
253#endif
254	/* Console */
255	consinit();
256
257	/* Load memory to UVM */
258	kernend = atop(round_page(SH3_P1SEG_TO_PHYS(end)));
259	physmem = atop(IOM_RAM_SIZE);
260	uvm_page_physload(
261		kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE),
262		kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE),
263		VM_FREELIST_DEFAULT);
264
265	/* Initialize proc0 u-area */
266	sh_proc0_init();
267
268	/* Initialize pmap and start to address translation */
269	pmap_bootstrap();
270
271#	/*
272	 * XXX We can't return here, because we change stack pointer.
273	 *     So jump to return address directly.
274	 */
275	__asm volatile (
276		"jmp	@%0;"
277		"mov	%1, r15"
278		:: "r"(pc),"r"(lwp0.l_md.md_pcb->pcb_sf.sf_r7_bank));
279}
280
281/*
282 * consinit:
283 * initialize the system console.
284 * XXX - shouldn't deal with this initted thing, but then,
285 * it shouldn't be called from init386 either.
286 */
287void
288consinit()
289{
290	static int initted;
291
292	if (initted)
293		return;
294	initted = 1;
295
296	cninit();
297}
298
299int
300bus_space_map (t, addr, size, flags, bshp)
301	bus_space_tag_t t;
302	bus_addr_t addr;
303	bus_size_t size;
304	int flags;
305	bus_space_handle_t *bshp;
306{
307
308	*bshp = (bus_space_handle_t)addr;
309
310	return 0;
311}
312
313int
314sh_memio_subregion(t, bsh, offset, size, nbshp)
315	bus_space_tag_t t;
316	bus_space_handle_t bsh;
317	bus_size_t offset, size;
318	bus_space_handle_t *nbshp;
319{
320
321	*nbshp = bsh + offset;
322	return (0);
323}
324
325int
326sh_memio_alloc(t, rstart, rend, size, alignment, boundary, flags,
327	       bpap, bshp)
328	bus_space_tag_t t;
329	bus_addr_t rstart, rend;
330	bus_size_t size, alignment, boundary;
331	int flags;
332	bus_addr_t *bpap;
333	bus_space_handle_t *bshp;
334{
335	*bshp = *bpap = rstart;
336
337	return (0);
338}
339
340void
341sh_memio_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
342{
343
344}
345
346void
347sh_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
348{
349	return;
350}
351
352#ifdef SH4_PCMCIA
353
354int
355shpcmcia_memio_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp)
356{
357	int error;
358	struct extent *ex;
359	bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT;
360
361	if (pt != SH3_BUS_SPACE_PCMCIA_IO &&
362	    pt != SH3_BUS_SPACE_PCMCIA_MEM &&
363	    pt != SH3_BUS_SPACE_PCMCIA_ATT) {
364		*bshp = (bus_space_handle_t)bpa;
365
366		return 0;
367	}
368
369	ex = iomem_ex;
370
371#if 0
372	/*
373	 * Before we go any further, let's make sure that this
374	 * region is available.
375	 */
376	error = extent_alloc_region(ex, bpa, size,
377				    EX_NOWAIT | EX_MALLOCOK );
378	if (error){
379		printf("sh3_pcmcia_memio_map:extent_alloc_region error\n");
380		return (error);
381	}
382#endif
383
384	/*
385	 * For memory space, map the bus physical address to
386	 * a kernel virtual address.
387	 */
388	error = shpcmcia_mem_add_mapping(bpa, size, (int)t, bshp );
389#if 0
390	if (error) {
391		if (extent_free(ex, bpa, size, EX_NOWAIT | EX_MALLOCOK )) {
392			printf("sh3_pcmcia_memio_map: pa 0x%lx, size 0x%lx\n",
393			       bpa, size);
394			printf("sh3_pcmcia_memio_map: can't free region\n");
395		}
396	}
397#endif
398
399	return (error);
400}
401
402int
403shpcmcia_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int type, bus_space_handle_t *bshp)
404{
405	u_long pa, endpa;
406	vaddr_t va;
407	pt_entry_t *pte;
408	unsigned int m = 0;
409	int io_type = type & ~SH3_BUS_SPACE_PCMCIA_8BIT;
410
411	pa = sh3_trunc_page(bpa);
412	endpa = sh3_round_page(bpa + size);
413
414#ifdef DIAGNOSTIC
415	if (endpa <= pa)
416		panic("sh3_pcmcia_mem_add_mapping: overflow");
417#endif
418
419	va = uvm_km_alloc(kernel_map, endpa - pa, 0,
420	    UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
421	if (va == 0){
422		printf("shpcmcia_add_mapping: nomem \n");
423		return (ENOMEM);
424	}
425
426	*bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
427
428#define MODE(t, s)							\
429	(t) & SH3_BUS_SPACE_PCMCIA_8BIT ?				\
430		_PG_PCMCIA_ ## s ## 8 :					\
431		_PG_PCMCIA_ ## s ## 16
432	switch (io_type) {
433	default:
434		panic("unknown pcmcia space.");
435		/* NOTREACHED */
436	case SH3_BUS_SPACE_PCMCIA_IO:
437		m = MODE(type, IO);
438		break;
439	case SH3_BUS_SPACE_PCMCIA_MEM:
440		m = MODE(type, MEM);
441		break;
442	case SH3_BUS_SPACE_PCMCIA_ATT:
443		m = MODE(type, ATTR);
444		break;
445	}
446#undef MODE
447
448	for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
449		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
450		pte = __pmap_kpte_lookup(va);
451		KDASSERT(pte);
452		*pte |= m;  /* PTEA PCMCIA assistant bit */
453		sh_tlb_update(0, va, *pte);
454	}
455
456	return 0;
457}
458
459void
460shpcmcia_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
461{
462	struct extent *ex;
463	u_long va, endva;
464	bus_addr_t bpa;
465	bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT;
466
467	if (pt != SH3_BUS_SPACE_PCMCIA_IO &&
468	    pt != SH3_BUS_SPACE_PCMCIA_MEM &&
469	    pt != SH3_BUS_SPACE_PCMCIA_ATT) {
470		return ;
471	}
472
473	ex = iomem_ex;
474
475	va = sh3_trunc_page(bsh);
476	endva = sh3_round_page(bsh + size);
477
478#ifdef DIAGNOSTIC
479	if (endva <= va)
480		panic("sh3_pcmcia_memio_unmap: overflow");
481#endif
482
483	pmap_extract(pmap_kernel(), va, &bpa);
484	bpa += bsh & PGOFSET;
485
486	/*
487	 * Free the kernel virtual mapping.
488	 */
489	pmap_kremove(va, endva - va);
490	pmap_update(pmap_kernel());
491	uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY);
492
493#if 0
494	if (extent_free(ex, bpa, size,
495			EX_NOWAIT | EX_MALLOCOK)) {
496		printf("sh3_pcmcia_memio_unmap: %s 0x%lx, size 0x%lx\n",
497		       "pa", bpa, size);
498		printf("sh3_pcmcia_memio_unmap: can't free region\n");
499	}
500#endif
501}
502
503void
504shpcmcia_memio_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size)
505{
506
507	/* sh3_pcmcia_memio_unmap() does all that we need to do. */
508	shpcmcia_memio_unmap(t, bsh, size);
509}
510
511int
512shpcmcia_memio_subregion(t, bsh, offset, size, nbshp)
513	bus_space_tag_t t;
514	bus_space_handle_t bsh;
515	bus_size_t offset, size;
516	bus_space_handle_t *nbshp;
517{
518
519	*nbshp = bsh + offset;
520	return (0);
521}
522
523#endif /* SH4_PCMCIA */
524
525#if !defined(DONT_INIT_BSC)
526/*
527 * InitializeBsc
528 * : BSC(Bus State Controller)
529 */
530void InitializeBsc(void);
531
532void
533InitializeBsc()
534{
535
536	/*
537	 * Drive RAS,CAS in stand by mode and bus release mode
538	 * Area0 = Normal memory, Area5,6=Normal(no burst)
539	 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory
540	 * Area4 = Normal Memory
541	 * Area6 = Normal memory
542	 */
543#if defined(SH3)
544	_reg_write_2(SH3_BCR1, BSC_BCR1_VAL);
545#elif defined(SH4)
546	_reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
547#endif
548
549	/*
550	 * Bus Width
551	 * Area4: Bus width = 16bit
552	 * Area6,5 = 16bit
553	 * Area1 = 8bit
554	 * Area2,3: Bus width = 32bit
555	 */
556	_reg_write_2(SH_(BCR2), BSC_BCR2_VAL);
557
558	/*
559	 * Idle cycle number in transition area and read to write
560	 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3
561	 * Area1 = 3, Area0 = 3
562	 */
563#if defined(SH3)
564	_reg_write_2(SH3_WCR1, BSC_WCR1_VAL);
565#elif defined(SH4)
566	_reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
567#endif
568
569	/*
570	 * Wait cycle
571	 * Area 6 = 6
572	 * Area 5 = 2
573	 * Area 4 = 10
574	 * Area 3 = 3
575	 * Area 2,1 = 3
576	 * Area 0 = 6
577	 */
578#if defined(SH3)
579	_reg_write_2(SH3_WCR2, BSC_WCR2_VAL);
580#elif defined(SH4)
581	_reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
582#endif
583
584#if defined(SH4) && defined(BSC_WCR3_VAL)
585	_reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
586#endif
587
588	/*
589	 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle,
590	 * write pre-charge=1cycle
591	 * CAS before RAS refresh RAS assert time = 3 cycle
592	 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON
593	 * CAS before RAS refresh ON, EDO DRAM
594	 */
595#if defined(SH3)
596	_reg_write_2(SH3_MCR, BSC_MCR_VAL);
597#elif defined(SH4)
598	_reg_write_4(SH4_MCR, BSC_MCR_VAL);
599#endif
600
601#if defined(BSC_SDMR2_VAL)
602	_reg_write_1(BSC_SDMR2_VAL, 0);
603#endif
604
605#if defined(BSC_SDMR3_VAL)
606#if !(defined(COMPUTEXEVB) && defined(SH7709A))
607	_reg_write_1(BSC_SDMR3_VAL, 0);
608#else
609	_reg_write_2(0x1a000000, 0);	/* ADDSET */
610	_reg_write_1(BSC_SDMR3_VAL, 0);
611	_reg_write_2(0x18000000, 0);	/* ADDRST */
612#endif /* !(COMPUTEXEVB && SH7709A) */
613#endif /* BSC_SDMR3_VAL */
614
615	/*
616	 * PCMCIA Control Register
617	 * OE/WE assert delay 3.5 cycle
618	 * OE/WE negate-address delay 3.5 cycle
619	 */
620#ifdef BSC_PCR_VAL
621	_reg_write_2(SH_(PCR), BSC_PCR_VAL);
622#endif
623
624	/*
625	 * Refresh Timer Control/Status Register
626	 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt
627	 * Count Limit = 1024
628	 * In following statement, the reason why high byte = 0xa5(a4 in RFCR)
629	 * is the rule of SH3 in writing these register.
630	 */
631	_reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL);
632
633	/*
634	 * Refresh Timer Counter
635	 * Initialize to 0
636	 */
637#ifdef BSC_RTCNT_VAL
638	_reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL);
639#endif
640
641	/* set Refresh Time Constant Register */
642	_reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL);
643
644	/* init Refresh Count Register */
645#ifdef BSC_RFCR_VAL
646	_reg_write_2(SH_(RFCR), BSC_RFCR_VAL);
647#endif
648
649	/*
650	 * Clock Pulse Generator
651	 */
652	/* Set Clock mode (make internal clock double speed) */
653	_reg_write_2(SH_(FRQCR), FRQCR_VAL);
654
655	/*
656	 * Cache
657	 */
658#ifndef CACHE_DISABLE
659	/* Cache ON */
660	_reg_write_4(SH_(CCR), 0x1);
661#endif
662}
663#endif /* !DONT_INIT_BSC */
664
665
666 /* XXX This value depends on physical available memory */
667#define OSIMAGE_BUF_ADDR	(IOM_RAM_BEGIN + 0x00400000)
668
669void
670LoadAndReset(const char *osimage)
671{
672	void *buf_addr;
673	u_long size;
674	const u_long *src;
675	u_long *dest;
676	u_long csum = 0;
677	u_long csum2 = 0;
678	u_long size2;
679
680	printf("LoadAndReset: copy start\n");
681	buf_addr = (void *)OSIMAGE_BUF_ADDR;
682
683	size = *(const u_long *)osimage;
684	src = (const u_long *)osimage;
685	dest = buf_addr;
686
687	size = (size + sizeof(u_long) * 2 + 3) >> 2;
688	size2 = size;
689
690	while (size--) {
691		csum += *src;
692		*dest++ = *src++;
693	}
694
695	dest = buf_addr;
696	while (size2--)
697		csum2 += *dest++;
698
699	printf("LoadAndReset: copy end[%lx,%lx]\n", csum, csum2);
700	printf("start XLoadAndReset\n");
701
702	/* mask all externel interrupt (XXX) */
703
704	XLoadAndReset(buf_addr);
705}
706
707void
708intc_intr(int ssr, int spc, int ssp)
709{
710	struct intc_intrhand *ih;
711	struct clockframe cf;
712	int s, evtcode;
713
714	switch (cpu_product) {
715	case CPU_PRODUCT_7708:
716	case CPU_PRODUCT_7708S:
717	case CPU_PRODUCT_7708R:
718		evtcode = _reg_read_4(SH3_INTEVT);
719		break;
720	case CPU_PRODUCT_7709:
721	case CPU_PRODUCT_7709A:
722		evtcode = _reg_read_4(SH7709_INTEVT2);
723		break;
724	case CPU_PRODUCT_7750:
725	case CPU_PRODUCT_7750S:
726		evtcode = _reg_read_4(SH4_INTEVT);
727		break;
728	default:
729#ifdef DIAGNOSTIC
730		panic("intr_intc: cpu_product %d unhandled!", cpu_product);
731#endif
732		return;
733	}
734
735	ih = EVTCODE_IH(evtcode);
736	KDASSERT(ih->ih_func);
737	/*
738	 * On entry, all interrrupts are disabled,
739	 * and exception is enabled for P3 access. (kernel stack is P3,
740	 * SH3 may or may not cause TLB miss when access stack.)
741	 * Enable higher level interrupt here.
742	 */
743	s = _cpu_intr_resume(ih->ih_level);
744
745	switch (evtcode) {
746	default:
747		(*ih->ih_func)(ih->ih_arg);
748		break;
749	case SH_INTEVT_TMU0_TUNI0:
750		cf.spc = spc;
751		cf.ssr = ssr;
752		cf.ssp = ssp;
753		(*ih->ih_func)(&cf);
754		break;
755	case SH_INTEVT_NMI:
756		printf("NMI ignored.\n");
757		break;
758	}
759}
760
761