arm_arch.h revision 1.1 
1/* -*-C++-*-	$NetBSD: arm_arch.h,v 1.1 2001/02/09 18:34:50 uch Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 *    must display the following acknowledgement:
20 *        This product includes software developed by the NetBSD
21 *        Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 *    contributors may be used to endorse or promote products derived
24 *    from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef _HPCBOOT_ARM_ARCH_H_
40#define _HPCBOOT_ARM_ARCH_H_
41
42#include <hpcboot.h>
43#include <arch.h>
44
45class Console;
46
47class ARMArchitecture : public Architecture {
48private:
49	int _kmode;
50	// test routine for SA-1100 peripherals.
51	void testFramebuffer(void);
52	void testUART(void);
53
54public:
55	ARMArchitecture(Console *&, MemoryManager *&);
56	virtual ~ARMArchitecture(void);
57
58	BOOL init(void);
59	BOOL setupLoader(void);
60	void systemInfo(void);
61	void jump(paddr_t info, paddr_t pvce);
62};
63
64__BEGIN_DECLS
65// Coprocessor 15
66u_int32_t GetCop15Reg0(void);
67u_int32_t GetCop15Reg1(void);	void SetCop15Reg1(u_int32_t);
68u_int32_t GetCop15Reg2(void);	void SetCop15Reg2(u_int32_t);
69u_int32_t GetCop15Reg3(void);	void SetCop15Reg3(u_int32_t);
70u_int32_t GetCop15Reg5(void);
71u_int32_t GetCop15Reg6(void);
72u_int32_t GetCop15Reg13(void);	void SetCop15Reg13(u_int32_t);
73u_int32_t GetCop15Reg14(void);
74
75// Interrupt
76void EI(void);
77void DI(void);
78
79// Write-Back I/D-separate Cache
80void InvalidateICache(void);
81void WritebackDCache(void);
82void InvalidateDCache(void);
83void WritebackInvalidateDCache(void);
84
85// MMU TLB access
86void FlushIDTLB(void);
87void FlushITLB(void);
88void FlushDTLB(void);
89void FlushDTLBS(vaddr_t);
90
91u_int32_t GetCPSR(void);
92void SetCPSR(u_int32_t);
93void SetSVCMode(void);
94void SetSystemMode(void);
95
96// 2nd bootloader
97void boot_func(kaddr_t, kaddr_t, kaddr_t, kaddr_t);
98extern char boot_func_end[];
99#define BOOT_FUNC_START		reinterpret_cast <vaddr_t>(boot_func)
100#define BOOT_FUNC_END		reinterpret_cast <vaddr_t>(boot_func_end)
101
102/* jump to 2nd loader */
103void FlatJump(kaddr_t, kaddr_t, kaddr_t, kaddr_t);
104__END_DECLS
105
106#endif // _HPCBOOT_ARM_ARCH_H_
107