arm_arch.h revision 1.5 
1/* -*-C++-*-	$NetBSD: arm_arch.h,v 1.5 2008/03/08 02:26:03 rafal Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 *    must display the following acknowledgement:
20 *        This product includes software developed by the NetBSD
21 *        Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 *    contributors may be used to endorse or promote products derived
24 *    from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef _HPCBOOT_ARM_ARCH_H_
40#define	_HPCBOOT_ARM_ARCH_H_
41
42#include <hpcboot.h>
43#include <arch.h>
44
45class Console;
46
47class ARMArchitecture : public Architecture {
48protected:
49	int _kmode;
50	// test routine for SA-1100 peripherals.
51	virtual void testFramebuffer(void) = 0;
52	virtual void testUART(void) = 0;
53
54public:
55	ARMArchitecture(Console *&, MemoryManager *&);
56	virtual ~ARMArchitecture(void);
57
58	virtual BOOL init(void) = 0;
59	void systemInfo(void);
60
61	virtual BOOL setupLoader(void) = 0;
62	virtual void jump(paddr_t info, paddr_t pvec) = 0;
63};
64
65__BEGIN_DECLS
66// Coprocessor 15
67uint32_t GetCop15Reg0(void);
68uint32_t GetCop15Reg1(void);	void SetCop15Reg1(uint32_t);
69uint32_t GetCop15Reg2(void);	void SetCop15Reg2(uint32_t);
70uint32_t GetCop15Reg3(void);	void SetCop15Reg3(uint32_t);
71uint32_t GetCop15Reg5(void);
72uint32_t GetCop15Reg6(void);
73uint32_t GetCop15Reg13(void);	void SetCop15Reg13(uint32_t);
74uint32_t GetCop15Reg14(void);
75
76// Interrupt
77void EI(void);
78void DI(void);
79
80// Write-Back I/D-separate Cache
81void InvalidateICache(void);
82void WritebackDCache(void);
83void InvalidateDCache(void);
84void WritebackInvalidateDCache(void);
85
86// MMU TLB access
87void FlushIDTLB(void);
88void FlushITLB(void);
89void FlushDTLB(void);
90void FlushDTLBS(vaddr_t);
91
92uint32_t GetCPSR(void);
93void SetCPSR(uint32_t);
94void SetSVCMode(void);
95void SetSystemMode(void);
96
97__END_DECLS
98
99#endif // _HPCBOOT_ARM_ARCH_H_
100