tx3912videoreg.h revision 1.1
1 /* $NetBSD: tx3912videoreg.h,v 1.1 1999/11/20 19:56:31 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* 29 * TOSHIBA TMPR3912/05, Philips PR31700 Video module register 30 */ 31 #define TX3912_VIDEOCTRL1_REG 0x28 32 #define TX3912_VIDEOCTRL2_REG 0x2c 33 #define TX3912_VIDEOCTRL3_REG 0x30 34 #define TX3912_VIDEOCTRL4_REG 0x34 35 #define TX3912_VIDEOCTRL5_REG 0x38 36 #define TX3912_VIDEOCTRL6_REG 0x3c 37 #define TX3912_VIDEOCTRL7_REG 0x40 38 #define TX3912_VIDEOCTRL8_REG 0x44 39 #define TX3912_VIDEOCTRL9_REG 0x48 40 #define TX3912_VIDEOCTRL10_REG 0x4c 41 #define TX3912_VIDEOCTRL11_REG 0x50 42 #define TX3912_VIDEOCTRL12_REG 0x54 43 #define TX3912_VIDEOCTRL13_REG 0x58 44 #define TX3912_VIDEOCTRL14_REG 0x5c 45 46 #define TX3912_FRAMEBUFFER_ALIGNMENT 16 47 #define TX3912_FRAMEBUFFER_BOUNDARY 0x100000 48 #define TX3912_FRAMEBUFFER_MAX (2048 * 1024 * 8) 49 50 /* 51 * Video Control 1 Register 52 */ 53 /* R */ 54 #define TX3912_VIDEOCTRL1_LINECNT_SHIFT 22 55 #define TX3912_VIDEOCTRL1_LINECNT_MASK 0x3ff 56 #define TX3912_VIDEOCTRL1_LINECNT(cr) \ 57 (((cr) >> TX3912_VIDEOCTRL1_LINECNT_SHIFT) & \ 58 TX3912_VIDEOCTRL1_LINECNT_MASK) 59 /* R/W */ 60 #define TX3912_VIDEOCTRL1_LOADDLY 0x00200000 61 /* R/W */ 62 /* 63 * CP Rate = 36.864MHz / (BAUDVAL * 2 + 2) 64 */ 65 #define TX3912_VIDEOCTRL1_BAUDVAL_SHIFT 16 66 #define TX3912_VIDEOCTRL1_BAUDVAL_MASK 0x1f 67 #define TX3912_VIDEOCTRL1_BAUDVAL(cr) \ 68 (((cr) >> TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 69 TX3912_VIDEOCTRL1_BAUDVAL_MASK) 70 #define TX3912_VIDEOCTRL1_BAUDVAL_SET(cr, val) \ 71 ((cr) | (((val) << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 72 (TX3912_VIDEOCTRL1_BAUDVAL_MASK << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT))) 73 74 /* R/W */ 75 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT 9 76 #define TX3912_VIDEOCTRL1_VIDDONEVAL_MASK 0x7f 77 #define TX3912_VIDEOCTRL1_VIDDONEVAL(cr) \ 78 (((cr) >> TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 79 TX3912_VIDEOCTRL1_VIDDONEVAL_MASK) 80 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SET(cr, val) \ 81 ((cr) | (((val) << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 82 (TX3912_VIDEOCTRL1_VIDDONEVAL_MASK << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT))) 83 /* R/W */ 84 #define TX3912_VIDEOCTRL1_ENFREEZEFRAME 0x00000100 85 /* R/W */ 86 #define TX3912_VIDEOCTRL1_BITSEL_SHIFT 6 87 #define TX3912_VIDEOCTRL1_BITSEL_MASK 0x3 88 #define TX3912_VIDEOCTRL1_BITSEL(cr) \ 89 (((cr) >> TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 90 TX3912_VIDEOCTRL1_BITSEL_MASK) 91 #define TX3912_VIDEOCTRL1_BITSEL_SET(cr, val) \ 92 ((cr) | (((val) << TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 93 (TX3912_VIDEOCTRL1_BITSEL_MASK << TX3912_VIDEOCTRL1_BITSEL_SHIFT))) 94 #define TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR 0x3 95 #define TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE 0x2 96 #define TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE 0x1 97 #define TX3912_VIDEOCTRL1_BITSEL_MONOCHROME 0x0 98 /* R/W */ 99 #define TX3912_VIDEOCTRL1_DISPSPLIT 0x00000020 100 #define TX3912_VIDEOCTRL1_DISP8 0x00000010 101 #define TX3912_VIDEOCTRL1_DFMODE 0x00000008 102 #define TX3912_VIDEOCTRL1_INVVID 0x00000004 103 #define TX3912_VIDEOCTRL1_DISPON 0x00000002 104 #define TX3912_VIDEOCTRL1_ENVID 0x00000001 105 106 /* 107 * Video Control 2 Register 108 */ 109 /* W */ 110 #define TX3912_VIDEOCTRL2_VIDRATE_SHIFT 22 111 #define TX3912_VIDEOCTRL2_VIDRATE_MASK 0x3ff 112 #define TX3912_VIDEOCTRL2_VIDRATE(cr) \ 113 (((cr) >> TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 114 TX3912_VIDEOCTRL2_VIDRATE_MASK) 115 #define TX3912_VIDEOCTRL2_VIDRATE_SET(cr, val) \ 116 ((cr) | (((val) << TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 117 (TX3912_VIDEOCTRL2_VIDRATE_MASK << TX3912_VIDEOCTRL2_VIDRATE_SHIFT))) 118 119 /* W */ 120 /* 121 * HORZVAL = (HorzSize4 - 1) for 4bit split or non-split LCD 122 * HORZVAL = (HorzSize8 - 1) for 8bit non-split LCD 123 */ 124 #define TX3912_VIDEOCTRL2_HORZVAL_SHIFT 12 125 #define TX3912_VIDEOCTRL2_HORZVAL_MASK 0x1ff 126 #define TX3912_VIDEOCTRL2_HORZVAL(cr) \ 127 (((cr) >> TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 128 TX3912_VIDEOCTRL2_HORZVAL_MASK) 129 #define TX3912_VIDEOCTRL2_HORZVAL_SET(cr, val) \ 130 ((cr) | (((val) << TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 131 (TX3912_VIDEOCTRL2_HORZVAL_MASK << TX3912_VIDEOCTRL2_HORZVAL_SHIFT))) 132 133 /* W */ 134 /* 135 * LINEVAL = (# of Lines - 1) for a non-split LCD 136 * LINEVAL = (# of Lins2 - 1) for a split LCD 137 */ 138 #define TX3912_VIDEOCTRL2_LINEVAL_SHIFT 0 139 #define TX3912_VIDEOCTRL2_LINEVAL_MASK 0x3ff 140 #define TX3912_VIDEOCTRL2_LINEVAL(cr) \ 141 (((cr) >> TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 142 TX3912_VIDEOCTRL2_LINEVAL_MASK) 143 #define TX3912_VIDEOCTRL2_LINEVAL_SET(cr, val) \ 144 ((cr) | (((val) << TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 145 (TX3912_VIDEOCTRL2_LINEVAL_MASK << TX3912_VIDEOCTRL2_LINEVAL_SHIFT))) 146 147 /* 148 * Video Control 3 Register 149 */ 150 /* W */ 151 #define TX3912_VIDEOCTRL3_VIDBANK_SHIFT 20 152 #define TX3912_VIDEOCTRL3_VIDBANK_MASK 0xfff 153 #define TX3912_VIDEOCTRL3_VIDBANK(cr) \ 154 (((cr) >> TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 155 TX3912_VIDEOCTRL3_VIDBANK_MASK) 156 #define TX3912_VIDEOCTRL3_VIDBANK_SET(cr, val) \ 157 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 158 (TX3912_VIDEOCTRL3_VIDBANK_MASK << TX3912_VIDEOCTRL3_VIDBANK_SHIFT))) 159 160 /* W */ 161 #define TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT 4 162 #define TX3912_VIDEOCTRL3_VIDBASEHI_MASK 0xffff 163 #define TX3912_VIDEOCTRL3_VIDBASEHI(cr) \ 164 (((cr) >> TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 165 TX3912_VIDEOCTRL3_VIDBASEHI_MASK) 166 #define TX3912_VIDEOCTRL3_VIDBASEHI_SET(cr, val) \ 167 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 168 (TX3912_VIDEOCTRL3_VIDBASEHI_MASK << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT))) 169 170 171 /* 172 * Video Control 4 Register 173 */ 174 /* W */ 175 /* 176 * DF Rate = LineRate / (DFVAL + 1) 177 */ 178 #define TX3912_VIDEOCTRL4_DFVAL_SHIFT 24 179 #define TX3912_VIDEOCTRL4_DFVAL_MASK 0xff 180 #define TX3912_VIDEOCTRL4_DFVAL(cr) \ 181 (((cr) >> TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 182 TX3912_VIDEOCTRL4_DFVAL_MASK) 183 #define TX3912_VIDEOCTRL4_DFVAL_SET(cr, val) \ 184 ((cr) | (((val) << TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 185 (TX3912_VIDEOCTRL4_DFVAL_MASK << TX3912_VIDEOCTRL4_DFVAL_SHIFT))) 186 187 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT 20 188 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK 0xf 189 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL(cr) \ 190 (((cr) >> TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 191 TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK) 192 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SET(cr, val) \ 193 ((cr) | (((val) << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 194 (TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT))) 195 196 #define TX3912_VIDEOCTRL4_VIDBASELO_SHIFT 4 197 #define TX3912_VIDEOCTRL4_VIDBASELO_MASK 0xffff 198 #define TX3912_VIDEOCTRL4_VIDBASELO(cr) \ 199 (((cr) >> TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 200 TX3912_VIDEOCTRL4_VIDBASELO_MASK) 201 #define TX3912_VIDEOCTRL4_VIDBASELO_SET(cr, val) \ 202 ((cr) | (((val) << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 203 (TX3912_VIDEOCTRL4_VIDBASELO_MASK << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT))) 204 205 /* 206 * Video Control 5 Register 207 */ 208 /* W */ 209 /* 210 * TX3912_VIDEOCTRL5_REDSEL (31:0) 211 */ 212 213 /* 214 * Video Control 6 Register 215 */ 216 /* W */ 217 /* 218 * TX3912_VIDEOCTRL6_GREENSEL (31:0) 219 */ 220 221 /* 222 * Video Control 7 Register 223 */ 224 /* W */ 225 /* 226 * TX3912_VIDEOCTRL6_BLUESEL (31:0) 227 */ 228 229 /* 230 * Video Control 8 Register 231 */ 232 /* W */ 233 /* 234 * 2_3 means `2 out of 3' 235 */ 236 #define TX3912_VIDEOCTRL8_PAT2_3_SHIFT 0 237 #define TX3912_VIDEOCTRL8_PAT2_3_MASK 0xfff 238 #define TX3912_VIDEOCTRL8_PAT2_3(cr) \ 239 (((cr) >> TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 240 TX3912_VIDEOCTRL8_PAT2_3_MASK) 241 #define TX3912_VIDEOCTRL8_PAT2_3_SET(cr, val) \ 242 ((cr) | (((val) << TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 243 (TX3912_VIDEOCTRL8_PAT2_3_MASK << TX3912_VIDEOCTRL8_PAT2_3_SHIFT))) 244 245 /* 246 * Video Control 9 Register 247 */ 248 /* W */ 249 #define TX3912_VIDEOCTRL9_PAT3_4_SHIFT 16 250 #define TX3912_VIDEOCTRL9_PAT3_4_MASK 0xffff 251 #define TX3912_VIDEOCTRL9_PAT3_4(cr) \ 252 (((cr) >> TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 253 TX3912_VIDEOCTRL9_PAT3_4_MASK) 254 #define TX3912_VIDEOCTRL9_PAT3_4_SET(cr, val) \ 255 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 256 (TX3912_VIDEOCTRL9_PAT3_4_MASK << TX3912_VIDEOCTRL9_PAT3_4_SHIFT))) 257 /* W */ 258 #define TX3912_VIDEOCTRL9_PAT2_4_SHIFT 0 259 #define TX3912_VIDEOCTRL9_PAT2_4_MASK 0xffff 260 #define TX3912_VIDEOCTRL9_PAT2_4(cr) \ 261 (((cr) >> TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 262 TX3912_VIDEOCTRL9_PAT2_4_MASK) 263 #define TX3912_VIDEOCTRL9_PAT2_4_SET(cr, val) \ 264 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 265 (TX3912_VIDEOCTRL9_PAT2_4_MASK << TX3912_VIDEOCTRL9_PAT2_4_SHIFT))) 266 267 /* 268 * Video Control 10 Register 269 */ 270 /* W */ 271 #define TX3912_VIDEOCTRL10_PAT4_5_SHIFT 0 272 #define TX3912_VIDEOCTRL10_PAT4_5_MASK 0xfffff 273 #define TX3912_VIDEOCTRL10_PAT4_5(cr) \ 274 (((cr) >> TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 275 TX3912_VIDEOCTRL10_PAT4_5_MASK) 276 #define TX3912_VIDEOCTRL10_PAT4_5_SET(cr, val) \ 277 ((cr) | (((val) << TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 278 (TX3912_VIDEOCTRL10_PAT4_5_MASK << TX3912_VIDEOCTRL10_PAT4_5_SHIFT))) 279 280 /* 281 * Video Control 11 Register 282 */ 283 /* W */ 284 #define TX3912_VIDEOCTRL11_PAT3_5_SHIFT 0 285 #define TX3912_VIDEOCTRL11_PAT3_5_MASK 0xfffff 286 #define TX3912_VIDEOCTRL11_PAT3_5(cr) \ 287 (((cr) >> TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 288 TX3912_VIDEOCTRL11_PAT3_5_MASK) 289 #define TX3912_VIDEOCTRL11_PAT3_5_SET(cr, val) \ 290 ((cr) | (((val) << TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 291 (TX3912_VIDEOCTRL11_PAT3_5_MASK << TX3912_VIDEOCTRL11_PAT3_5_SHIFT))) 292 293 /* 294 * Video Control 12 Register 295 */ 296 /* W */ 297 #define TX3912_VIDEOCTRL12_PAT6_7_SHIFT 0 298 #define TX3912_VIDEOCTRL12_PAT6_7_MASK 0xfffffff 299 #define TX3912_VIDEOCTRL12_PAT6_7(cr) \ 300 (((cr) >> TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 301 TX3912_VIDEOCTRL12_PAT6_7_MASK) 302 #define TX3912_VIDEOCTRL12_PAT6_7_SET(cr, val) \ 303 ((cr) | (((val) << TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 304 (TX3912_VIDEOCTRL12_PAT6_7_MASK << TX3912_VIDEOCTRL12_PAT6_7_SHIFT))) 305 306 /* 307 * Video Control 13 Register 308 */ 309 /* W */ 310 #define TX3912_VIDEOCTRL13_PAT5_7_SHIFT 0 311 #define TX3912_VIDEOCTRL13_PAT5_7_MASK 0xfffffff 312 #define TX3912_VIDEOCTRL13_PAT5_7(cr) \ 313 (((cr) >> TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 314 TX3912_VIDEOCTRL13_PAT5_7_MASK) 315 #define TX3912_VIDEOCTRL13_PAT5_7_SET(cr, val) \ 316 ((cr) | (((val) << TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 317 (TX3912_VIDEOCTRL13_PAT5_7_MASK << TX3912_VIDEOCTRL13_PAT5_7_SHIFT))) 318 319 /* 320 * Video Control 14 Register 321 */ 322 /* W */ 323 #define TX3912_VIDEOCTRL14_PAT4_7_SHIFT 0 324 #define TX3912_VIDEOCTRL14_PAT4_7_MASK 0xfffffff 325 #define TX3912_VIDEOCTRL14_PAT4_7(cr) \ 326 (((cr) >> TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 327 TX3912_VIDEOCTRL14_PAT4_7_MASK) 328 #define TX3912_VIDEOCTRL14_PAT4_7_SET(cr, val) \ 329 ((cr) | (((val) << TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 330 (TX3912_VIDEOCTRL14_PAT4_7_MASK << TX3912_VIDEOCTRL14_PAT4_7_SHIFT))) 331 332 333
Indexes created Sun Nov 02 07:10:05 GMT 2025