tx3912videoreg.h revision 1.3
1 /* $NetBSD: tx3912videoreg.h,v 1.3 2000/05/08 21:57:58 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 /* 29 * TOSHIBA TMPR3912/05, Philips PR31700 Video module register 30 */ 31 #define TX3912_VIDEOCTRL1_REG 0x28 32 #define TX3912_VIDEOCTRL2_REG 0x2c 33 #define TX3912_VIDEOCTRL3_REG 0x30 34 #define TX3912_VIDEOCTRL4_REG 0x34 35 #define TX3912_VIDEOCTRL5_REG 0x38 36 #define TX3912_VIDEOCTRL6_REG 0x3c 37 #define TX3912_VIDEOCTRL7_REG 0x40 38 #define TX3912_VIDEOCTRL8_REG 0x44 39 #define TX3912_VIDEOCTRL9_REG 0x48 40 #define TX3912_VIDEOCTRL10_REG 0x4c 41 #define TX3912_VIDEOCTRL11_REG 0x50 42 #define TX3912_VIDEOCTRL12_REG 0x54 43 #define TX3912_VIDEOCTRL13_REG 0x58 44 #define TX3912_VIDEOCTRL14_REG 0x5c 45 46 #define TX3912_FRAMEBUFFER_ALIGNMENT 16 47 #define TX3912_FRAMEBUFFER_BOUNDARY 0x100000 48 #define TX3912_FRAMEBUFFER_MAX (2048 * 1024 * 8) 49 50 /* 51 * Video Control 1 Register 52 */ 53 /* R */ 54 #define TX3912_VIDEOCTRL1_LINECNT_SHIFT 22 55 #define TX3912_VIDEOCTRL1_LINECNT_MASK 0x3ff 56 #define TX3912_VIDEOCTRL1_LINECNT(cr) \ 57 (((cr) >> TX3912_VIDEOCTRL1_LINECNT_SHIFT) & \ 58 TX3912_VIDEOCTRL1_LINECNT_MASK) 59 /* R/W */ 60 #define TX3912_VIDEOCTRL1_LOADDLY 0x00200000 61 /* R/W */ 62 /* 63 * CP Rate = 36.864MHz / (BAUDVAL * 2 + 2) 64 */ 65 #define TX3912_VIDEOCTRL1_BAUDVAL_SHIFT 16 66 #define TX3912_VIDEOCTRL1_BAUDVAL_MASK 0x1f 67 #define TX3912_VIDEOCTRL1_BAUDVAL(cr) \ 68 (((cr) >> TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 69 TX3912_VIDEOCTRL1_BAUDVAL_MASK) 70 #define TX3912_VIDEOCTRL1_BAUDVAL_SET(cr, val) \ 71 ((cr) | (((val) << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 72 (TX3912_VIDEOCTRL1_BAUDVAL_MASK << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT))) 73 74 /* R/W */ 75 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT 9 76 #define TX3912_VIDEOCTRL1_VIDDONEVAL_MASK 0x7f 77 #define TX3912_VIDEOCTRL1_VIDDONEVAL(cr) \ 78 (((cr) >> TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 79 TX3912_VIDEOCTRL1_VIDDONEVAL_MASK) 80 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SET(cr, val) \ 81 ((cr) | (((val) << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 82 (TX3912_VIDEOCTRL1_VIDDONEVAL_MASK << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT))) 83 /* R/W */ 84 #define TX3912_VIDEOCTRL1_ENFREEZEFRAME 0x00000100 85 /* R/W */ 86 #define TX3912_VIDEOCTRL1_BITSEL_SHIFT 6 87 #define TX3912_VIDEOCTRL1_BITSEL_MASK 0x3 88 #define TX3912_VIDEOCTRL1_BITSEL(cr) \ 89 (((cr) >> TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 90 TX3912_VIDEOCTRL1_BITSEL_MASK) 91 #define TX3912_VIDEOCTRL1_BITSEL_CLR(cr) \ 92 ((cr) &= ~(TX3912_VIDEOCTRL1_BITSEL_MASK << \ 93 TX3912_VIDEOCTRL1_BITSEL_SHIFT)) 94 #define TX3912_VIDEOCTRL1_BITSEL_SET(cr, val) \ 95 ((cr) | (((val) << TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 96 (TX3912_VIDEOCTRL1_BITSEL_MASK << TX3912_VIDEOCTRL1_BITSEL_SHIFT))) 97 #define TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR 0x3 98 #define TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE 0x2 99 #define TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE 0x1 100 #define TX3912_VIDEOCTRL1_BITSEL_MONOCHROME 0x0 101 /* R/W */ 102 #define TX3912_VIDEOCTRL1_DISPSPLIT 0x00000020 103 #define TX3912_VIDEOCTRL1_DISP8 0x00000010 104 #define TX3912_VIDEOCTRL1_DFMODE 0x00000008 105 #define TX3912_VIDEOCTRL1_INVVID 0x00000004 106 #define TX3912_VIDEOCTRL1_DISPON 0x00000002 107 #define TX3912_VIDEOCTRL1_ENVID 0x00000001 108 109 /* 110 * Video Control 2 Register 111 */ 112 /* W */ 113 #define TX3912_VIDEOCTRL2_VIDRATE_SHIFT 22 114 #define TX3912_VIDEOCTRL2_VIDRATE_MASK 0x3ff 115 #define TX3912_VIDEOCTRL2_VIDRATE(cr) \ 116 (((cr) >> TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 117 TX3912_VIDEOCTRL2_VIDRATE_MASK) 118 #define TX3912_VIDEOCTRL2_VIDRATE_SET(cr, val) \ 119 ((cr) | (((val) << TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 120 (TX3912_VIDEOCTRL2_VIDRATE_MASK << TX3912_VIDEOCTRL2_VIDRATE_SHIFT))) 121 122 /* W */ 123 /* 124 * HORZVAL = (HorzSize4 - 1) for 4bit split or non-split LCD 125 * HORZVAL = (HorzSize8 - 1) for 8bit non-split LCD 126 */ 127 #define TX3912_VIDEOCTRL2_HORZVAL_SHIFT 12 128 #define TX3912_VIDEOCTRL2_HORZVAL_MASK 0x1ff 129 #define TX3912_VIDEOCTRL2_HORZVAL(cr) \ 130 (((cr) >> TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 131 TX3912_VIDEOCTRL2_HORZVAL_MASK) 132 #define TX3912_VIDEOCTRL2_HORZVAL_SET(cr, val) \ 133 ((cr) | (((val) << TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 134 (TX3912_VIDEOCTRL2_HORZVAL_MASK << TX3912_VIDEOCTRL2_HORZVAL_SHIFT))) 135 136 /* W */ 137 /* 138 * LINEVAL = (# of Lines - 1) for a non-split LCD 139 * LINEVAL = (# of Lins2 - 1) for a split LCD 140 */ 141 #define TX3912_VIDEOCTRL2_LINEVAL_SHIFT 0 142 #define TX3912_VIDEOCTRL2_LINEVAL_MASK 0x3ff 143 #define TX3912_VIDEOCTRL2_LINEVAL(cr) \ 144 (((cr) >> TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 145 TX3912_VIDEOCTRL2_LINEVAL_MASK) 146 #define TX3912_VIDEOCTRL2_LINEVAL_SET(cr, val) \ 147 ((cr) | (((val) << TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 148 (TX3912_VIDEOCTRL2_LINEVAL_MASK << TX3912_VIDEOCTRL2_LINEVAL_SHIFT))) 149 150 /* 151 * Video Control 3 Register 152 */ 153 /* W */ 154 #define TX3912_VIDEOCTRL3_VIDBANK_SHIFT 20 155 #define TX3912_VIDEOCTRL3_VIDBANK_MASK 0xfff 156 #define TX3912_VIDEOCTRL3_VIDBANK(cr) \ 157 (((cr) >> TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 158 TX3912_VIDEOCTRL3_VIDBANK_MASK) 159 #define TX3912_VIDEOCTRL3_VIDBANK_SET(cr, val) \ 160 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 161 (TX3912_VIDEOCTRL3_VIDBANK_MASK << TX3912_VIDEOCTRL3_VIDBANK_SHIFT))) 162 163 /* W */ 164 #define TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT 4 165 #define TX3912_VIDEOCTRL3_VIDBASEHI_MASK 0xffff 166 #define TX3912_VIDEOCTRL3_VIDBASEHI(cr) \ 167 (((cr) >> TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 168 TX3912_VIDEOCTRL3_VIDBASEHI_MASK) 169 #define TX3912_VIDEOCTRL3_VIDBASEHI_SET(cr, val) \ 170 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 171 (TX3912_VIDEOCTRL3_VIDBASEHI_MASK << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT))) 172 173 174 /* 175 * Video Control 4 Register 176 */ 177 /* W */ 178 /* 179 * DF Rate = LineRate / (DFVAL + 1) 180 */ 181 #define TX3912_VIDEOCTRL4_DFVAL_SHIFT 24 182 #define TX3912_VIDEOCTRL4_DFVAL_MASK 0xff 183 #define TX3912_VIDEOCTRL4_DFVAL(cr) \ 184 (((cr) >> TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 185 TX3912_VIDEOCTRL4_DFVAL_MASK) 186 #define TX3912_VIDEOCTRL4_DFVAL_SET(cr, val) \ 187 ((cr) | (((val) << TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 188 (TX3912_VIDEOCTRL4_DFVAL_MASK << TX3912_VIDEOCTRL4_DFVAL_SHIFT))) 189 190 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT 20 191 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK 0xf 192 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL(cr) \ 193 (((cr) >> TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 194 TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK) 195 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SET(cr, val) \ 196 ((cr) | (((val) << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 197 (TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT))) 198 199 #define TX3912_VIDEOCTRL4_VIDBASELO_SHIFT 4 200 #define TX3912_VIDEOCTRL4_VIDBASELO_MASK 0xffff 201 #define TX3912_VIDEOCTRL4_VIDBASELO(cr) \ 202 (((cr) >> TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 203 TX3912_VIDEOCTRL4_VIDBASELO_MASK) 204 #define TX3912_VIDEOCTRL4_VIDBASELO_SET(cr, val) \ 205 ((cr) | (((val) << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 206 (TX3912_VIDEOCTRL4_VIDBASELO_MASK << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT))) 207 208 /* 209 * Video Control 5 Register 210 */ 211 /* W */ 212 /* 213 * TX3912_VIDEOCTRL5_REDSEL (31:0) 214 */ 215 216 /* 217 * Video Control 6 Register 218 */ 219 /* W */ 220 /* 221 * TX3912_VIDEOCTRL6_GREENSEL (31:0) 222 */ 223 224 /* 225 * Video Control 7 Register 226 */ 227 /* W */ 228 /* 229 * TX3912_VIDEOCTRL6_BLUESEL (31:0) 230 */ 231 232 /* 233 * Video Control 8 Register 234 */ 235 /* W */ 236 /* 237 * 2_3 means `2 out of 3' 238 */ 239 #define TX3912_VIDEOCTRL8_PAT2_3_SHIFT 0 240 #define TX3912_VIDEOCTRL8_PAT2_3_MASK 0xfff 241 #define TX3912_VIDEOCTRL8_PAT2_3(cr) \ 242 (((cr) >> TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 243 TX3912_VIDEOCTRL8_PAT2_3_MASK) 244 #define TX3912_VIDEOCTRL8_PAT2_3_SET(cr, val) \ 245 ((cr) | (((val) << TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 246 (TX3912_VIDEOCTRL8_PAT2_3_MASK << TX3912_VIDEOCTRL8_PAT2_3_SHIFT))) 247 248 /* 249 * Video Control 9 Register 250 */ 251 /* W */ 252 #define TX3912_VIDEOCTRL9_PAT3_4_SHIFT 16 253 #define TX3912_VIDEOCTRL9_PAT3_4_MASK 0xffff 254 #define TX3912_VIDEOCTRL9_PAT3_4(cr) \ 255 (((cr) >> TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 256 TX3912_VIDEOCTRL9_PAT3_4_MASK) 257 #define TX3912_VIDEOCTRL9_PAT3_4_SET(cr, val) \ 258 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 259 (TX3912_VIDEOCTRL9_PAT3_4_MASK << TX3912_VIDEOCTRL9_PAT3_4_SHIFT))) 260 /* W */ 261 #define TX3912_VIDEOCTRL9_PAT2_4_SHIFT 0 262 #define TX3912_VIDEOCTRL9_PAT2_4_MASK 0xffff 263 #define TX3912_VIDEOCTRL9_PAT2_4(cr) \ 264 (((cr) >> TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 265 TX3912_VIDEOCTRL9_PAT2_4_MASK) 266 #define TX3912_VIDEOCTRL9_PAT2_4_SET(cr, val) \ 267 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 268 (TX3912_VIDEOCTRL9_PAT2_4_MASK << TX3912_VIDEOCTRL9_PAT2_4_SHIFT))) 269 270 /* 271 * Video Control 10 Register 272 */ 273 /* W */ 274 #define TX3912_VIDEOCTRL10_PAT4_5_SHIFT 0 275 #define TX3912_VIDEOCTRL10_PAT4_5_MASK 0xfffff 276 #define TX3912_VIDEOCTRL10_PAT4_5(cr) \ 277 (((cr) >> TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 278 TX3912_VIDEOCTRL10_PAT4_5_MASK) 279 #define TX3912_VIDEOCTRL10_PAT4_5_SET(cr, val) \ 280 ((cr) | (((val) << TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 281 (TX3912_VIDEOCTRL10_PAT4_5_MASK << TX3912_VIDEOCTRL10_PAT4_5_SHIFT))) 282 283 /* 284 * Video Control 11 Register 285 */ 286 /* W */ 287 #define TX3912_VIDEOCTRL11_PAT3_5_SHIFT 0 288 #define TX3912_VIDEOCTRL11_PAT3_5_MASK 0xfffff 289 #define TX3912_VIDEOCTRL11_PAT3_5(cr) \ 290 (((cr) >> TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 291 TX3912_VIDEOCTRL11_PAT3_5_MASK) 292 #define TX3912_VIDEOCTRL11_PAT3_5_SET(cr, val) \ 293 ((cr) | (((val) << TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 294 (TX3912_VIDEOCTRL11_PAT3_5_MASK << TX3912_VIDEOCTRL11_PAT3_5_SHIFT))) 295 296 /* 297 * Video Control 12 Register 298 */ 299 /* W */ 300 #define TX3912_VIDEOCTRL12_PAT6_7_SHIFT 0 301 #define TX3912_VIDEOCTRL12_PAT6_7_MASK 0xfffffff 302 #define TX3912_VIDEOCTRL12_PAT6_7(cr) \ 303 (((cr) >> TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 304 TX3912_VIDEOCTRL12_PAT6_7_MASK) 305 #define TX3912_VIDEOCTRL12_PAT6_7_SET(cr, val) \ 306 ((cr) | (((val) << TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 307 (TX3912_VIDEOCTRL12_PAT6_7_MASK << TX3912_VIDEOCTRL12_PAT6_7_SHIFT))) 308 309 /* 310 * Video Control 13 Register 311 */ 312 /* W */ 313 #define TX3912_VIDEOCTRL13_PAT5_7_SHIFT 0 314 #define TX3912_VIDEOCTRL13_PAT5_7_MASK 0xfffffff 315 #define TX3912_VIDEOCTRL13_PAT5_7(cr) \ 316 (((cr) >> TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 317 TX3912_VIDEOCTRL13_PAT5_7_MASK) 318 #define TX3912_VIDEOCTRL13_PAT5_7_SET(cr, val) \ 319 ((cr) | (((val) << TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 320 (TX3912_VIDEOCTRL13_PAT5_7_MASK << TX3912_VIDEOCTRL13_PAT5_7_SHIFT))) 321 322 /* 323 * Video Control 14 Register 324 */ 325 /* W */ 326 #define TX3912_VIDEOCTRL14_PAT4_7_SHIFT 0 327 #define TX3912_VIDEOCTRL14_PAT4_7_MASK 0xfffffff 328 #define TX3912_VIDEOCTRL14_PAT4_7(cr) \ 329 (((cr) >> TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 330 TX3912_VIDEOCTRL14_PAT4_7_MASK) 331 #define TX3912_VIDEOCTRL14_PAT4_7_SET(cr, val) \ 332 ((cr) | (((val) << TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 333 (TX3912_VIDEOCTRL14_PAT4_7_MASK << TX3912_VIDEOCTRL14_PAT4_7_SHIFT))) 334 335 /* 336 * Default dither pattern 337 */ 338 #define P0000 0x0 339 #define P0001 0x1 340 #define P0010 0x2 341 #define P0011 0x3 342 #define P0100 0x4 343 #define P0101 0x5 344 #define P0110 0x6 345 #define P0111 0x7 346 #define P1000 0x8 347 #define P1001 0x9 348 #define P1010 0xa 349 #define P1011 0xb 350 #define P1100 0xc 351 #define P1101 0xd 352 #define P1110 0xe 353 #define P1111 0xf 354 355 #define DITHER_PATTERN(p0, p1, p2, p3, p4, p5, p6) \ 356 (((p0) << 24) | ((p1) << 20) | ((p2) << 16) | ((p3) << 12) | \ 357 ((p4) << 8) | ((p5) << 4) || (p6)) 358 359 #define TX3912_VIDEOCTRL8_PAT2_3_DEFAULT \ 360 DITHER_PATTERN(0, 0, 0, 0, P0111, P1101, P1010) 361 #define TX3912_VIDEOCTRL9_PAT3_4_DEFAULT \ 362 DITHER_PATTERN(0, 0, 0, P0111, P1101, P1011, P1110) 363 #define TX3912_VIDEOCTRL9_PAT2_4_DEFAULT \ 364 DITHER_PATTERN(0, 0, 0, P1010, P0101, P1010, P0101) 365 #define TX3912_VIDEOCTRL10_PAT4_5_DEFAULT \ 366 DITHER_PATTERN(0, 0, P0111, P1101, P1111, P1011, P1111) 367 #define TX3912_VIDEOCTRL11_PAT3_5_DEFAULT \ 368 DITHER_PATTERN(0, 0, P0111, P1010, P0101, P1010, P1101) 369 #define TX3912_VIDEOCTRL12_PAT6_7_DEFAULT \ 370 DITHER_PATTERN(P1111, P1011, P1111, P1101, P1111, P1110, P0111) 371 #define TX3912_VIDEOCTRL13_PAT5_7_DEFAULT \ 372 DITHER_PATTERN(P0111, P1011, P0101, P1010, P1101, P1110, P1111) 373 #define TX3912_VIDEOCTRL14_PAT4_7_DEFAULT \ 374 DITHER_PATTERN(P1011, P1001, P1101, P1101, P1100, P0110, P0011) 375 376 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1 15 377 #define TX3912_VIDEO_DITHER_DUTYCYCLE_6_7 14 378 #define TX3912_VIDEO_DITHER_DUTYCYCLE_4_5 13 379 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_4 12 380 #define TX3912_VIDEO_DITHER_DUTYCYCLE_5_7 11 381 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_3 10 382 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_5 9 383 #define TX3912_VIDEO_DITHER_DUTYCYCLE_4_7 8 384 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_4 7 385 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_7 6 386 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_5 5 387 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_3 4 388 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_7 3 389 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_5 2 390 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_7 1 391 #define TX3912_VIDEO_DITHER_DUTYCYCLE_0 0 392
Indexes created Sun Nov 02 07:10:05 GMT 2025