tx3912videoreg.h revision 1.5
1 /* $NetBSD: tx3912videoreg.h,v 1.5 2001/06/14 11:09:55 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * TOSHIBA TMPR3912/05, Philips PR31700 Video module register 40 */ 41 #define TX3912_VIDEOCTRL1_REG 0x28 42 #define TX3912_VIDEOCTRL2_REG 0x2c 43 #define TX3912_VIDEOCTRL3_REG 0x30 44 #define TX3912_VIDEOCTRL4_REG 0x34 45 #define TX3912_VIDEOCTRL5_REG 0x38 46 #define TX3912_VIDEOCTRL6_REG 0x3c 47 #define TX3912_VIDEOCTRL7_REG 0x40 48 #define TX3912_VIDEOCTRL8_REG 0x44 49 #define TX3912_VIDEOCTRL9_REG 0x48 50 #define TX3912_VIDEOCTRL10_REG 0x4c 51 #define TX3912_VIDEOCTRL11_REG 0x50 52 #define TX3912_VIDEOCTRL12_REG 0x54 53 #define TX3912_VIDEOCTRL13_REG 0x58 54 #define TX3912_VIDEOCTRL14_REG 0x5c 55 56 #define TX3912_FRAMEBUFFER_ALIGNMENT 16 57 #define TX3912_FRAMEBUFFER_BOUNDARY 0x100000 58 #define TX3912_FRAMEBUFFER_MAX (2048 * 1024 * 8) 59 60 /* 61 * Video Control 1 Register 62 */ 63 /* R */ 64 #define TX3912_VIDEOCTRL1_LINECNT_SHIFT 22 65 #define TX3912_VIDEOCTRL1_LINECNT_MASK 0x3ff 66 #define TX3912_VIDEOCTRL1_LINECNT(cr) \ 67 (((cr) >> TX3912_VIDEOCTRL1_LINECNT_SHIFT) & \ 68 TX3912_VIDEOCTRL1_LINECNT_MASK) 69 /* R/W */ 70 #define TX3912_VIDEOCTRL1_LOADDLY 0x00200000 71 /* R/W */ 72 /* 73 * CP Rate = 36.864MHz / (BAUDVAL * 2 + 2) 74 */ 75 #define TX3912_VIDEOCTRL1_BAUDVAL_SHIFT 16 76 #define TX3912_VIDEOCTRL1_BAUDVAL_MASK 0x1f 77 #define TX3912_VIDEOCTRL1_BAUDVAL(cr) \ 78 (((cr) >> TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 79 TX3912_VIDEOCTRL1_BAUDVAL_MASK) 80 #define TX3912_VIDEOCTRL1_BAUDVAL_SET(cr, val) \ 81 ((cr) | (((val) << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 82 (TX3912_VIDEOCTRL1_BAUDVAL_MASK << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT))) 83 84 /* R/W */ 85 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT 9 86 #define TX3912_VIDEOCTRL1_VIDDONEVAL_MASK 0x7f 87 #define TX3912_VIDEOCTRL1_VIDDONEVAL(cr) \ 88 (((cr) >> TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 89 TX3912_VIDEOCTRL1_VIDDONEVAL_MASK) 90 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SET(cr, val) \ 91 ((cr) | (((val) << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 92 (TX3912_VIDEOCTRL1_VIDDONEVAL_MASK << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT))) 93 /* R/W */ 94 #define TX3912_VIDEOCTRL1_ENFREEZEFRAME 0x00000100 95 /* R/W */ 96 #define TX3912_VIDEOCTRL1_BITSEL_SHIFT 6 97 #define TX3912_VIDEOCTRL1_BITSEL_MASK 0x3 98 #define TX3912_VIDEOCTRL1_BITSEL(cr) \ 99 (((cr) >> TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 100 TX3912_VIDEOCTRL1_BITSEL_MASK) 101 #define TX3912_VIDEOCTRL1_BITSEL_CLR(cr) \ 102 ((cr) &= ~(TX3912_VIDEOCTRL1_BITSEL_MASK << \ 103 TX3912_VIDEOCTRL1_BITSEL_SHIFT)) 104 #define TX3912_VIDEOCTRL1_BITSEL_SET(cr, val) \ 105 ((cr) | (((val) << TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 106 (TX3912_VIDEOCTRL1_BITSEL_MASK << TX3912_VIDEOCTRL1_BITSEL_SHIFT))) 107 #define TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR 0x3 108 #define TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE 0x2 109 #define TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE 0x1 110 #define TX3912_VIDEOCTRL1_BITSEL_MONOCHROME 0x0 111 /* R/W */ 112 #define TX3912_VIDEOCTRL1_DISPSPLIT 0x00000020 113 #define TX3912_VIDEOCTRL1_DISP8 0x00000010 114 #define TX3912_VIDEOCTRL1_DFMODE 0x00000008 115 #define TX3912_VIDEOCTRL1_INVVID 0x00000004 116 #define TX3912_VIDEOCTRL1_DISPON 0x00000002 117 #define TX3912_VIDEOCTRL1_ENVID 0x00000001 118 119 /* 120 * Video Control 2 Register 121 */ 122 /* W */ 123 #define TX3912_VIDEOCTRL2_VIDRATE_SHIFT 22 124 #define TX3912_VIDEOCTRL2_VIDRATE_MASK 0x3ff 125 #define TX3912_VIDEOCTRL2_VIDRATE(cr) \ 126 (((cr) >> TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 127 TX3912_VIDEOCTRL2_VIDRATE_MASK) 128 #define TX3912_VIDEOCTRL2_VIDRATE_SET(cr, val) \ 129 ((cr) | (((val) << TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 130 (TX3912_VIDEOCTRL2_VIDRATE_MASK << TX3912_VIDEOCTRL2_VIDRATE_SHIFT))) 131 132 /* W */ 133 /* 134 * HORZVAL = (HorzSize4 - 1) for 4bit split or non-split LCD 135 * HORZVAL = (HorzSize8 - 1) for 8bit non-split LCD 136 */ 137 #define TX3912_VIDEOCTRL2_HORZVAL_SHIFT 12 138 #define TX3912_VIDEOCTRL2_HORZVAL_MASK 0x1ff 139 #define TX3912_VIDEOCTRL2_HORZVAL(cr) \ 140 (((cr) >> TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 141 TX3912_VIDEOCTRL2_HORZVAL_MASK) 142 #define TX3912_VIDEOCTRL2_HORZVAL_SET(cr, val) \ 143 ((cr) | (((val) << TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 144 (TX3912_VIDEOCTRL2_HORZVAL_MASK << TX3912_VIDEOCTRL2_HORZVAL_SHIFT))) 145 146 /* W */ 147 /* 148 * LINEVAL = (# of Lines - 1) for a non-split LCD 149 * LINEVAL = (# of Lins2 - 1) for a split LCD 150 */ 151 #define TX3912_VIDEOCTRL2_LINEVAL_SHIFT 0 152 #define TX3912_VIDEOCTRL2_LINEVAL_MASK 0x3ff 153 #define TX3912_VIDEOCTRL2_LINEVAL(cr) \ 154 (((cr) >> TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 155 TX3912_VIDEOCTRL2_LINEVAL_MASK) 156 #define TX3912_VIDEOCTRL2_LINEVAL_SET(cr, val) \ 157 ((cr) | (((val) << TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 158 (TX3912_VIDEOCTRL2_LINEVAL_MASK << TX3912_VIDEOCTRL2_LINEVAL_SHIFT))) 159 160 /* 161 * Video Control 3 Register 162 */ 163 /* W */ 164 #define TX3912_VIDEOCTRL3_VIDBANK_SHIFT 20 165 #define TX3912_VIDEOCTRL3_VIDBANK_MASK 0xfff 166 #define TX3912_VIDEOCTRL3_VIDBANK(cr) \ 167 (((cr) >> TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 168 TX3912_VIDEOCTRL3_VIDBANK_MASK) 169 #define TX3912_VIDEOCTRL3_VIDBANK_SET(cr, val) \ 170 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 171 (TX3912_VIDEOCTRL3_VIDBANK_MASK << TX3912_VIDEOCTRL3_VIDBANK_SHIFT))) 172 173 /* W */ 174 #define TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT 4 175 #define TX3912_VIDEOCTRL3_VIDBASEHI_MASK 0xffff 176 #define TX3912_VIDEOCTRL3_VIDBASEHI(cr) \ 177 (((cr) >> TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 178 TX3912_VIDEOCTRL3_VIDBASEHI_MASK) 179 #define TX3912_VIDEOCTRL3_VIDBASEHI_SET(cr, val) \ 180 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 181 (TX3912_VIDEOCTRL3_VIDBASEHI_MASK << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT))) 182 183 184 /* 185 * Video Control 4 Register 186 */ 187 /* W */ 188 /* 189 * DF Rate = LineRate / (DFVAL + 1) 190 */ 191 #define TX3912_VIDEOCTRL4_DFVAL_SHIFT 24 192 #define TX3912_VIDEOCTRL4_DFVAL_MASK 0xff 193 #define TX3912_VIDEOCTRL4_DFVAL(cr) \ 194 (((cr) >> TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 195 TX3912_VIDEOCTRL4_DFVAL_MASK) 196 #define TX3912_VIDEOCTRL4_DFVAL_SET(cr, val) \ 197 ((cr) | (((val) << TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 198 (TX3912_VIDEOCTRL4_DFVAL_MASK << TX3912_VIDEOCTRL4_DFVAL_SHIFT))) 199 200 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT 20 201 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK 0xf 202 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL(cr) \ 203 (((cr) >> TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 204 TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK) 205 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SET(cr, val) \ 206 ((cr) | (((val) << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 207 (TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT))) 208 209 #define TX3912_VIDEOCTRL4_VIDBASELO_SHIFT 4 210 #define TX3912_VIDEOCTRL4_VIDBASELO_MASK 0xffff 211 #define TX3912_VIDEOCTRL4_VIDBASELO(cr) \ 212 (((cr) >> TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 213 TX3912_VIDEOCTRL4_VIDBASELO_MASK) 214 #define TX3912_VIDEOCTRL4_VIDBASELO_SET(cr, val) \ 215 ((cr) | (((val) << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 216 (TX3912_VIDEOCTRL4_VIDBASELO_MASK << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT))) 217 218 /* 219 * Video Control 5 Register 220 */ 221 /* W */ 222 /* 223 * TX3912_VIDEOCTRL5_REDSEL (31:0) 224 */ 225 226 /* 227 * Video Control 6 Register 228 */ 229 /* W */ 230 /* 231 * TX3912_VIDEOCTRL6_GREENSEL (31:0) 232 */ 233 234 /* 235 * Video Control 7 Register 236 */ 237 /* W */ 238 /* 239 * TX3912_VIDEOCTRL6_BLUESEL (31:0) 240 */ 241 242 /* 243 * Video Control 8 Register 244 */ 245 /* W */ 246 /* 247 * 2_3 means `2 out of 3' 248 */ 249 #define TX3912_VIDEOCTRL8_PAT2_3_SHIFT 0 250 #define TX3912_VIDEOCTRL8_PAT2_3_MASK 0xfff 251 #define TX3912_VIDEOCTRL8_PAT2_3(cr) \ 252 (((cr) >> TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 253 TX3912_VIDEOCTRL8_PAT2_3_MASK) 254 #define TX3912_VIDEOCTRL8_PAT2_3_SET(cr, val) \ 255 ((cr) | (((val) << TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 256 (TX3912_VIDEOCTRL8_PAT2_3_MASK << TX3912_VIDEOCTRL8_PAT2_3_SHIFT))) 257 258 /* 259 * Video Control 9 Register 260 */ 261 /* W */ 262 #define TX3912_VIDEOCTRL9_PAT3_4_SHIFT 16 263 #define TX3912_VIDEOCTRL9_PAT3_4_MASK 0xffff 264 #define TX3912_VIDEOCTRL9_PAT3_4(cr) \ 265 (((cr) >> TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 266 TX3912_VIDEOCTRL9_PAT3_4_MASK) 267 #define TX3912_VIDEOCTRL9_PAT3_4_SET(cr, val) \ 268 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 269 (TX3912_VIDEOCTRL9_PAT3_4_MASK << TX3912_VIDEOCTRL9_PAT3_4_SHIFT))) 270 /* W */ 271 #define TX3912_VIDEOCTRL9_PAT2_4_SHIFT 0 272 #define TX3912_VIDEOCTRL9_PAT2_4_MASK 0xffff 273 #define TX3912_VIDEOCTRL9_PAT2_4(cr) \ 274 (((cr) >> TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 275 TX3912_VIDEOCTRL9_PAT2_4_MASK) 276 #define TX3912_VIDEOCTRL9_PAT2_4_SET(cr, val) \ 277 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 278 (TX3912_VIDEOCTRL9_PAT2_4_MASK << TX3912_VIDEOCTRL9_PAT2_4_SHIFT))) 279 280 /* 281 * Video Control 10 Register 282 */ 283 /* W */ 284 #define TX3912_VIDEOCTRL10_PAT4_5_SHIFT 0 285 #define TX3912_VIDEOCTRL10_PAT4_5_MASK 0xfffff 286 #define TX3912_VIDEOCTRL10_PAT4_5(cr) \ 287 (((cr) >> TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 288 TX3912_VIDEOCTRL10_PAT4_5_MASK) 289 #define TX3912_VIDEOCTRL10_PAT4_5_SET(cr, val) \ 290 ((cr) | (((val) << TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 291 (TX3912_VIDEOCTRL10_PAT4_5_MASK << TX3912_VIDEOCTRL10_PAT4_5_SHIFT))) 292 293 /* 294 * Video Control 11 Register 295 */ 296 /* W */ 297 #define TX3912_VIDEOCTRL11_PAT3_5_SHIFT 0 298 #define TX3912_VIDEOCTRL11_PAT3_5_MASK 0xfffff 299 #define TX3912_VIDEOCTRL11_PAT3_5(cr) \ 300 (((cr) >> TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 301 TX3912_VIDEOCTRL11_PAT3_5_MASK) 302 #define TX3912_VIDEOCTRL11_PAT3_5_SET(cr, val) \ 303 ((cr) | (((val) << TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 304 (TX3912_VIDEOCTRL11_PAT3_5_MASK << TX3912_VIDEOCTRL11_PAT3_5_SHIFT))) 305 306 /* 307 * Video Control 12 Register 308 */ 309 /* W */ 310 #define TX3912_VIDEOCTRL12_PAT6_7_SHIFT 0 311 #define TX3912_VIDEOCTRL12_PAT6_7_MASK 0xfffffff 312 #define TX3912_VIDEOCTRL12_PAT6_7(cr) \ 313 (((cr) >> TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 314 TX3912_VIDEOCTRL12_PAT6_7_MASK) 315 #define TX3912_VIDEOCTRL12_PAT6_7_SET(cr, val) \ 316 ((cr) | (((val) << TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 317 (TX3912_VIDEOCTRL12_PAT6_7_MASK << TX3912_VIDEOCTRL12_PAT6_7_SHIFT))) 318 319 /* 320 * Video Control 13 Register 321 */ 322 /* W */ 323 #define TX3912_VIDEOCTRL13_PAT5_7_SHIFT 0 324 #define TX3912_VIDEOCTRL13_PAT5_7_MASK 0xfffffff 325 #define TX3912_VIDEOCTRL13_PAT5_7(cr) \ 326 (((cr) >> TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 327 TX3912_VIDEOCTRL13_PAT5_7_MASK) 328 #define TX3912_VIDEOCTRL13_PAT5_7_SET(cr, val) \ 329 ((cr) | (((val) << TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 330 (TX3912_VIDEOCTRL13_PAT5_7_MASK << TX3912_VIDEOCTRL13_PAT5_7_SHIFT))) 331 332 /* 333 * Video Control 14 Register 334 */ 335 /* W */ 336 #define TX3912_VIDEOCTRL14_PAT4_7_SHIFT 0 337 #define TX3912_VIDEOCTRL14_PAT4_7_MASK 0xfffffff 338 #define TX3912_VIDEOCTRL14_PAT4_7(cr) \ 339 (((cr) >> TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 340 TX3912_VIDEOCTRL14_PAT4_7_MASK) 341 #define TX3912_VIDEOCTRL14_PAT4_7_SET(cr, val) \ 342 ((cr) | (((val) << TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 343 (TX3912_VIDEOCTRL14_PAT4_7_MASK << TX3912_VIDEOCTRL14_PAT4_7_SHIFT))) 344 345 /* 346 * Default dither pattern 347 */ 348 #define P0000 0x0 349 #define P0001 0x1 350 #define P0010 0x2 351 #define P0011 0x3 352 #define P0100 0x4 353 #define P0101 0x5 354 #define P0110 0x6 355 #define P0111 0x7 356 #define P1000 0x8 357 #define P1001 0x9 358 #define P1010 0xa 359 #define P1011 0xb 360 #define P1100 0xc 361 #define P1101 0xd 362 #define P1110 0xe 363 #define P1111 0xf 364 365 #define DITHER_PATTERN(p0, p1, p2, p3, p4, p5, p6) \ 366 (((p0) << 24) | ((p1) << 20) | ((p2) << 16) | ((p3) << 12) | \ 367 ((p4) << 8) | ((p5) << 4) || (p6)) 368 369 #define TX3912_VIDEOCTRL8_PAT2_3_DEFAULT \ 370 DITHER_PATTERN(0, 0, 0, 0, P0111, P1101, P1010) 371 #define TX3912_VIDEOCTRL9_PAT3_4_DEFAULT \ 372 DITHER_PATTERN(0, 0, 0, P0111, P1101, P1011, P1110) 373 #define TX3912_VIDEOCTRL9_PAT2_4_DEFAULT \ 374 DITHER_PATTERN(0, 0, 0, P1010, P0101, P1010, P0101) 375 #define TX3912_VIDEOCTRL10_PAT4_5_DEFAULT \ 376 DITHER_PATTERN(0, 0, P0111, P1101, P1111, P1011, P1110) 377 #define TX3912_VIDEOCTRL11_PAT3_5_DEFAULT \ 378 DITHER_PATTERN(0, 0, P0111, P1010, P0101, P1010, P1101) 379 #define TX3912_VIDEOCTRL12_PAT6_7_DEFAULT \ 380 DITHER_PATTERN(P1111, P1011, P1111, P1101, P1111, P1110, P0111) 381 #define TX3912_VIDEOCTRL13_PAT5_7_DEFAULT \ 382 DITHER_PATTERN(P0111, P1011, P0101, P1010, P1101, P1110, P1111) 383 #define TX3912_VIDEOCTRL14_PAT4_7_DEFAULT \ 384 DITHER_PATTERN(P1011, P1001, P1101, P1100, P0110, P0110, P0011) 385 386 /* dither duty cycle : pre-dithered data nible mapping */ 387 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1 15 388 #define TX3912_VIDEO_DITHER_DUTYCYCLE_6_7 14 389 #define TX3912_VIDEO_DITHER_DUTYCYCLE_4_5 13 390 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_4 12 391 #define TX3912_VIDEO_DITHER_DUTYCYCLE_5_7 11 392 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_3 10 393 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_5 9 394 #define TX3912_VIDEO_DITHER_DUTYCYCLE_4_7 8 395 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_4 7 396 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_7 6 397 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_5 5 398 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_3 4 399 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_7 3 400 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_5 2 401 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_7 1 402 #define TX3912_VIDEO_DITHER_DUTYCYCLE_0 0 403
Indexes created Sun Nov 02 07:10:05 GMT 2025