tx39icu.c revision 1.7
1 /* $NetBSD: tx39icu.c,v 1.7 2000/04/11 17:57:43 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "opt_use_poll.h" 30 #include "opt_tx39icudebug.h" 31 #include "opt_tx39_watchdogtimer.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 #define TAILQ_FOREACH(var, head, field) \ 39 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 40 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 41 42 #include <mips/cpuregs.h> 43 #include <machine/bus.h> 44 45 #include <hpcmips/tx/tx39var.h> 46 #include <hpcmips/tx/tx39icureg.h> 47 #include <hpcmips/tx/tx39clockvar.h> 48 49 #include <machine/clock_machdep.h> 50 #include <machine/cpu.h> 51 #include <dev/dec/clockvar.h> 52 53 #undef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT /* For explorer. good luck! */ 54 55 #ifdef TX39ICUDEBUG 56 #define DPRINTF(arg) printf arg 57 #else 58 #define DPRINTF(arg) 59 #endif 60 u_int32_t tx39intrvec; 61 62 /* IRQHIGH lines list */ 63 static const struct irqhigh_list { 64 int qh_pri; /* IRQHIGH priority */ 65 int qh_set; /* Register set */ 66 int qh_bit; /* bit offset in the register set */ 67 } irqhigh_list[] = { 68 {15, 5, 25}, /* POSPWROKINT */ 69 {15, 5, 24}, /* NEGPWROKINT */ 70 {14, 5, 30}, /* ALARMINT*/ 71 {13, 5, 29}, /* PERINT */ 72 #ifdef TX391X 73 {12, 2, 3}, /* MBUSPOSINT */ 74 {12, 2, 2}, /* MBUSNEGINT */ 75 {11, 2, 31}, /* UARTARXINT */ 76 {10, 2, 21}, /* UARTBRXINT */ 77 {9, 3, 19}, /* MFIOPOSINT19 */ 78 {9, 3, 18}, /* MFIOPOSINT18 */ 79 {9, 3, 17}, /* MFIOPOSINT17 */ 80 {9, 3, 16}, /* MFIOPOSINT16 */ 81 {8, 3, 1}, /* MFIOPOSINT1 */ 82 {8, 3, 0}, /* MFIOPOSINT0 */ 83 {8, 5, 13}, /* IOPOSINT6 */ 84 {8, 5, 12}, /* IOPOSINT5 */ 85 {7, 4, 19}, /* MFIONEGINT19 */ 86 {7, 4, 18}, /* MFIONEGINT18 */ 87 {7, 4, 17}, /* MFIONEGINT17 */ 88 {7, 4, 16}, /* MFIONEGINT16 */ 89 {6, 4, 1}, /* MFIONEGINT1 */ 90 {6, 4, 0}, /* MFIONEGINT0 */ 91 {6, 5, 6}, /* IONEGINT6 */ 92 {6, 5, 5}, /* IONEGINT5 */ 93 {5, 2, 5}, /* MBUSDMAFULLINT */ 94 #endif /* TX391X */ 95 #ifdef TX392X 96 {12, 2, 31}, /* UARTARXINT */ 97 {12, 2, 21}, /* UARTBRXINT */ 98 {11, 3, 19}, /* MFIOPOSINT19 */ 99 {11, 3, 18}, /* MFIOPOSINT18 */ 100 {11, 3, 17}, /* MFIOPOSINT17 */ 101 {11, 3, 16}, /* MFIOPOSINT16 */ 102 {10, 3, 1}, /* MFIOPOSINT1 */ 103 {10, 3, 0}, /* MFIOPOSINT0 */ 104 {10, 5, 13}, /* IOPOSINT6 */ 105 {10, 5, 12}, /* IOPOSINT5 */ 106 {9, 4, 19}, /* MFIONEGINT19 */ 107 {9, 4, 18}, /* MFIONEGINT18 */ 108 {9, 4, 17}, /* MFIONEGINT17 */ 109 {9, 4, 16}, /* MFIONEGINT16 */ 110 {8, 4, 1}, /* MFIONEGINT1 */ 111 {8, 4, 0}, /* MFIONEGINT0 */ 112 {8, 5, 6}, /* IONEGINT6 */ 113 {8, 5, 5}, /* IONEGINT5 */ 114 {5, 7, 19}, /* IRRXCINT */ 115 {5, 7, 17}, /* IRRXEINT */ 116 #endif /* TX392X */ 117 {4, 1, 18}, /* SNDDMACNTINT */ 118 {3, 1, 17}, /* TELDMACNTINT */ 119 {2, 1, 27}, /* CHIDMACNTINT */ 120 {1, 5, 7}, /* IOPOSINT0 */ 121 {1, 5, 0} /* IONEGINT0 */ 122 }; 123 124 struct txintr_high_entry { 125 int he_set; 126 txreg_t he_mask; 127 int (*he_fun) __P((void*)); 128 void *he_arg; 129 TAILQ_ENTRY(txintr_high_entry) he_link; 130 }; 131 132 #ifdef USE_POLL 133 struct txpoll_entry{ 134 int p_cnt; /* dispatch interval */ 135 int p_desc; 136 int (*p_fun) __P((void*)); 137 void *p_arg; 138 TAILQ_ENTRY(txpoll_entry) p_link; 139 }; 140 int tx39_poll_intr __P((void*)); 141 #endif /* USE_POLL */ 142 143 struct tx39icu_softc { 144 struct device sc_dev; 145 tx_chipset_tag_t sc_tc; 146 /* IRQLOW */ 147 txreg_t sc_le_mask[TX39_INTRSET_MAX + 1]; 148 int (*sc_le_fun[TX39_INTRSET_MAX + 1][32]) __P((void*)); 149 void *sc_le_arg[TX39_INTRSET_MAX + 1][32]; 150 /* IRQHIGH */ 151 TAILQ_HEAD(, txintr_high_entry) sc_he_head[TX39_IRQHIGH_MAX]; 152 /* Register */ 153 txreg_t sc_regs[TX39_INTRSET_MAX + 1]; 154 #ifdef USE_POLL 155 unsigned sc_pollcnt; 156 int sc_polling; 157 void *sc_poll_ih; 158 TAILQ_HEAD(, txpoll_entry) sc_p_head; 159 #endif /* USE_POLL */ 160 }; 161 162 int tx39icu_match __P((struct device*, struct cfdata*, void*)); 163 void tx39icu_attach __P((struct device*, struct device*, void*)); 164 int tx39icu_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 165 166 void tx39_intr_dump __P((struct tx39icu_softc*)); 167 void tx39_intr_decode __P((int, int*, int*)); 168 void tx39_irqhigh_disestablish __P((tx_chipset_tag_t, int, int, int)); 169 void tx39_irqhigh_establish __P((tx_chipset_tag_t, int, int, int, 170 int (*) __P((void*)), void*)); 171 void tx39_irqhigh_intr __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 172 int tx39_irqhigh __P((int, int)); 173 174 struct cfattach tx39icu_ca = { 175 sizeof(struct tx39icu_softc), tx39icu_match, tx39icu_attach 176 }; 177 178 int 179 tx39icu_match(parent, cf, aux) 180 struct device *parent; 181 struct cfdata *cf; 182 void *aux; 183 { 184 return 2; /* 1st attach group of txsim */ 185 } 186 187 void 188 tx39icu_attach(parent, self, aux) 189 struct device *parent; 190 struct device *self; 191 void *aux; 192 { 193 struct txsim_attach_args *ta = aux; 194 struct tx39icu_softc *sc = (void*)self; 195 tx_chipset_tag_t tc = ta->ta_tc; 196 txreg_t reg; 197 int i; 198 199 printf("\n"); 200 sc->sc_tc = ta->ta_tc; 201 202 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 203 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 204 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 205 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 206 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 207 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 208 #ifdef TX392X 209 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 210 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 211 #endif 212 #ifdef TX39ICUDEBUG 213 printf("\t[Windows CE setting]\n"); 214 tx39_intr_dump(sc); 215 #endif /* TX39ICUDEBUG */ 216 217 #ifdef WINCE_DEFAULT_SETTING 218 #warning WINCE_DEFAULT_SETTING 219 #else /* WINCE_DEFAULT_SETTING */ 220 /* Disable IRQLOW */ 221 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0); 222 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0); 223 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0); 224 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0); 225 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0); 226 #ifdef TX392X 227 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0); 228 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0); 229 #endif /* TX392X */ 230 231 /* Disable IRQHIGH */ 232 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 233 reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK; 234 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 235 #endif /* WINCE_DEFAULT_SETTING */ 236 237 /* Clear all pending interrupts */ 238 tx_conf_write(tc, TX39_INTRCLEAR1_REG, 239 tx_conf_read(tc, TX39_INTRSTATUS1_REG)); 240 tx_conf_write(tc, TX39_INTRCLEAR2_REG, 241 tx_conf_read(tc, TX39_INTRSTATUS2_REG)); 242 tx_conf_write(tc, TX39_INTRCLEAR3_REG, 243 tx_conf_read(tc, TX39_INTRSTATUS3_REG)); 244 tx_conf_write(tc, TX39_INTRCLEAR4_REG, 245 tx_conf_read(tc, TX39_INTRSTATUS4_REG)); 246 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 247 tx_conf_read(tc, TX39_INTRSTATUS5_REG)); 248 #ifdef TX392X 249 tx_conf_write(tc, TX39_INTRCLEAR7_REG, 250 tx_conf_read(tc, TX39_INTRSTATUS7_REG)); 251 tx_conf_write(tc, TX39_INTRCLEAR8_REG, 252 tx_conf_read(tc, TX39_INTRSTATUS8_REG)); 253 #endif /* TX392X */ 254 255 /* Enable global interrupts */ 256 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 257 reg |= TX39_INTRENABLE6_GLOBALEN; 258 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 259 260 /* Initialize IRQHIGH interrupt handler holder*/ 261 for (i = 0; i < TX39_IRQHIGH_MAX; i++) { 262 TAILQ_INIT(&sc->sc_he_head[i]); 263 } 264 #ifdef USE_POLL 265 /* Initialize polling handler holder */ 266 TAILQ_INIT(&sc->sc_p_head); 267 #endif /* USE_POLL */ 268 269 /* Register interrupt module myself */ 270 tx_conf_register_intr(tc, self); 271 } 272 273 int 274 tx39icu_intr(status, cause, pc, ipending) 275 u_int32_t status, cause, pc, ipending; 276 { 277 struct tx39icu_softc *sc; 278 tx_chipset_tag_t tc; 279 txreg_t reg, pend; 280 int i, j; 281 282 tc = tx_conf_get_tag(); 283 sc = tc->tc_intrt; 284 /* 285 * Read regsiter ASAP 286 */ 287 sc->sc_regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 288 sc->sc_regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 289 sc->sc_regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 290 sc->sc_regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 291 sc->sc_regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 292 sc->sc_regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 293 #ifdef TX392X 294 sc->sc_regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 295 sc->sc_regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 296 #endif 297 298 #ifdef TX39ICUDEBUG 299 if (!(ipending & MIPS_INT_MASK_4) && !(ipending & MIPS_INT_MASK_2)) { 300 bitdisp(ipending); 301 panic("bogus HwInt"); 302 } 303 #ifdef TX39_DEBUG 304 if (tx39debugflag) { 305 tx39_intr_dump(sc); 306 } 307 #endif 308 #endif /* TX39ICUDEBUG */ 309 310 /* IRQHIGH */ 311 if (ipending & MIPS_INT_MASK_4) { 312 tx39_irqhigh_intr(ipending, pc, status, cause); 313 314 return 0; 315 } 316 317 /* IRQLOW */ 318 if (ipending & MIPS_INT_MASK_2) { 319 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 320 int ofs; 321 #ifdef TX392X 322 if (i == 6) 323 continue; 324 #endif /* TX392X */ 325 ofs = TX39_INTRSTATUS_REG(i); 326 pend = sc->sc_regs[i]; 327 reg = sc->sc_le_mask[i] & pend; 328 /* Clear interrupts */ 329 tx_conf_write(tc, ofs, reg); 330 /* Dispatch handler */ 331 for (j = 0 ; j < 32; j++) { 332 if ((reg & (1 << j)) && 333 sc->sc_le_fun[i][j]) { 334 #ifdef TX39_DEBUG 335 tx39intrvec = (i << 16) | j; 336 if (tx39debugflag) { 337 DPRINTF(("IRQLOW %d:%d\n", 338 i, j)); 339 } 340 #endif /* TX39_DEBUG */ 341 (*sc->sc_le_fun[i][j]) 342 (sc->sc_le_arg[i][j]); 343 344 } 345 } 346 #ifdef TX39ICUDEBUG_PRINT_PENDING_INTERRUPT 347 pend &= ~reg; 348 if (pend) { 349 printf("%d pending:", i); 350 __bitdisp(pend, 0, 31, 0, 1); 351 } 352 #endif 353 354 } 355 } 356 #ifdef TX39_WATCHDOGTIMER 357 { 358 extern int tx39biu_intr __P((void*)); 359 /* Bus error (If watch dog timer is enabled)*/ 360 if (ipending & MIPS_INT_MASK_1) { 361 tx39biu_intr(0); /* Clear bus error */ 362 } 363 } 364 #endif 365 #if 0 366 /* reset priority mask */ 367 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 368 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff); 369 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 370 #endif 371 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 372 } 373 374 int 375 tx39_irqhigh(set, bit) 376 int set, bit; 377 { 378 int i, n; 379 380 n = sizeof irqhigh_list / sizeof (struct irqhigh_list); 381 for (i = 0; i < n; i++) { 382 if (irqhigh_list[i].qh_set == set && 383 irqhigh_list[i].qh_bit == bit) 384 return irqhigh_list[i].qh_pri; 385 } 386 387 return 0; 388 } 389 390 void 391 tx39_irqhigh_intr(ipending, pc, status, cause) 392 u_int32_t ipending; 393 u_int32_t pc; 394 u_int32_t status; 395 u_int32_t cause; 396 { 397 struct txintr_high_entry *he; 398 struct tx39icu_softc *sc; 399 struct clockframe cf; 400 tx_chipset_tag_t tc; 401 int i, pri, ofs, set; 402 txreg_t he_mask; 403 404 tc = tx_conf_get_tag(); 405 sc = tc->tc_intrt; 406 pri = TX39_INTRSTATUS6_INTVECT(sc->sc_regs[0]); 407 408 if (pri == TX39_INTRPRI13_TIMER_PERIODIC) { 409 tx_conf_write(tc, TX39_INTRCLEAR5_REG, 410 TX39_INTRSTATUS5_PERINT); 411 cf.pc = pc; 412 cf.sr = status; 413 hardclock(&cf); 414 intrcnt[HARDCLOCK]++; 415 416 return; 417 } 418 419 /* Handle all pending IRQHIGH interrupts */ 420 for (i = pri; i > 0; i--) { 421 TAILQ_FOREACH(he, &sc->sc_he_head[i], he_link) { 422 set = he->he_set; 423 he_mask = he->he_mask; 424 if (he_mask & (sc->sc_regs[set])) { 425 ofs = TX39_INTRSTATUS_REG(set); 426 /* Clear interrupt */ 427 tx_conf_write(tc, ofs, he_mask); 428 #ifdef TX39_DEBUG 429 tx39intrvec = (set << 16) | 430 (ffs(he_mask) - 1); 431 if (tx39debugflag) { 432 DPRINTF(("IRQHIGH: %d:%d\n", 433 set, ffs(he_mask) - 1)); 434 } 435 #endif /* TX39_DEBUG */ 436 /* Dispatch handler */ 437 (*he->he_fun)(he->he_arg); 438 } 439 } 440 } 441 } 442 443 void 444 tx39_intr_decode(intr, set, bit) 445 int intr; 446 int *set; 447 int *bit; 448 { 449 if (!intr || intr >= (TX39_INTRSET_MAX + 1) * 32 450 #ifdef TX392X 451 || intr == 6 452 #endif /* TX392X */ 453 ) { 454 panic("tx39icu_decode: bogus intrrupt line. %d", intr); 455 } 456 *set = intr / 32; 457 *bit = intr % 32; 458 } 459 460 void 461 tx39_irqhigh_establish(tc, set, bit, pri, ih_fun, ih_arg) 462 tx_chipset_tag_t tc; 463 int set; 464 int bit; 465 int pri; 466 int (*ih_fun) __P((void*)); 467 void *ih_arg; 468 { 469 struct tx39icu_softc *sc; 470 struct txintr_high_entry *he; 471 txreg_t reg; 472 473 sc = tc->tc_intrt; 474 /* 475 * Add new entry to `pri' priority 476 */ 477 if (!(he = malloc(sizeof(struct txintr_high_entry), 478 M_DEVBUF, M_NOWAIT))) { 479 panic ("tx39_irqhigh_establish: no memory."); 480 } 481 memset(he, 0, sizeof(struct txintr_high_entry)); 482 he->he_set = set; 483 he->he_mask= (1 << bit); 484 he->he_fun = ih_fun; 485 he->he_arg = ih_arg; 486 TAILQ_INSERT_TAIL(&sc->sc_he_head[pri], he, he_link); 487 /* 488 * Enable interrupt on this priority. 489 */ 490 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 491 reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri)); 492 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 493 } 494 495 void 496 tx39_irqhigh_disestablish(tc, set, bit, pri) 497 tx_chipset_tag_t tc; 498 int set, bit, pri; 499 { 500 struct tx39icu_softc *sc; 501 struct txintr_high_entry *he; 502 txreg_t reg; 503 504 sc = tc->tc_intrt; 505 TAILQ_FOREACH(he, &sc->sc_he_head[pri], he_link) { 506 if (he->he_set == set && he->he_mask == (1 << bit)) { 507 TAILQ_REMOVE(&sc->sc_he_head[pri], he, he_link); 508 free(he, M_DEVBUF); 509 break; 510 } 511 } 512 513 if (TAILQ_EMPTY(&sc->sc_he_head[pri])) { 514 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 515 reg &= ~(1 << pri); 516 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg); 517 } 518 } 519 520 521 void* 522 tx_intr_establish(tc, line, mode, level, ih_fun, ih_arg) 523 tx_chipset_tag_t tc; 524 int line; 525 int mode; /* Trigger setting. but TX39 handles edge only. */ 526 int level; /* XXX not yet */ 527 int (*ih_fun) __P((void*)); 528 void *ih_arg; 529 { 530 struct tx39icu_softc *sc; 531 txreg_t reg; 532 int bit, set, highpri, ofs; 533 534 sc = tc->tc_intrt; 535 536 tx39_intr_decode(line, &set, &bit); 537 538 sc->sc_le_fun[set][bit] = ih_fun; 539 sc->sc_le_arg[set][bit] = ih_arg; 540 DPRINTF(("tx_intr_establish: %d:%d", set, bit)); 541 542 if ((highpri = tx39_irqhigh(set, bit))) { 543 tx39_irqhigh_establish(tc, set, bit, highpri, 544 ih_fun, ih_arg); 545 DPRINTF(("(high)\n")); 546 } else { 547 /* Set mask for acknowledge. */ 548 sc->sc_le_mask[set] |= (1 << bit); 549 /* Enable interrupt */ 550 ofs = TX39_INTRENABLE_REG(set); 551 reg = tx_conf_read(tc, ofs); 552 reg |= (1 << bit); 553 tx_conf_write(tc, ofs, reg); 554 DPRINTF(("(low)\n")); 555 } 556 557 return (void*)line; 558 } 559 560 void 561 tx_intr_disestablish(tc, arg) 562 tx_chipset_tag_t tc; 563 void *arg; 564 { 565 struct tx39icu_softc *sc; 566 int set, bit, highpri, ofs; 567 txreg_t reg; 568 569 sc = tc->tc_intrt; 570 571 tx39_intr_decode((int)arg, &set, &bit); 572 DPRINTF(("tx_intr_disestablish: %d:%d", set, bit)); 573 574 if ((highpri = tx39_irqhigh(set, bit))) { 575 tx39_irqhigh_disestablish(tc, set, bit, highpri); 576 DPRINTF(("(high)\n")); 577 } else { 578 sc->sc_le_fun[set][bit] = 0; 579 sc->sc_le_arg[set][bit] = 0; 580 sc->sc_le_mask[set] &= ~(1 << bit); 581 ofs = TX39_INTRENABLE_REG(set); 582 reg = tx_conf_read(tc, ofs); 583 reg &= ~(1 << bit); 584 tx_conf_write(tc, ofs, reg); 585 DPRINTF(("(low)\n")); 586 } 587 } 588 589 u_int32_t 590 tx_intr_status(tc, r) 591 tx_chipset_tag_t tc; 592 int r; 593 { 594 struct tx39icu_softc *sc = tc->tc_intrt; 595 596 if (r < 0 || r >= TX39_INTRSET_MAX + 1) 597 panic("tx_intr_status: invalid index %d", r); 598 599 return (u_int32_t)(sc->sc_regs[r]); 600 } 601 602 #ifdef USE_POLL 603 void* 604 tx39_poll_establish(tc, interval, level, ih_fun, ih_arg) 605 tx_chipset_tag_t tc; 606 int interval; 607 int level; /* XXX not yet */ 608 int (*ih_fun) __P((void*)); 609 void *ih_arg; 610 { 611 struct tx39icu_softc *sc; 612 struct txpoll_entry *p; 613 int s; 614 void *ret; 615 616 s = splhigh(); 617 sc = tc->tc_intrt; 618 619 if (!(p = malloc(sizeof(struct txpoll_entry), 620 M_DEVBUF, M_NOWAIT))) { 621 panic ("tx39_poll_establish: no memory."); 622 } 623 memset(p, 0, sizeof(struct txpoll_entry)); 624 625 p->p_fun = ih_fun; 626 p->p_arg = ih_arg; 627 p->p_cnt = interval; 628 629 if (!sc->sc_polling) { 630 tx39clock_alarm_set(tc, 33); /* 33 msec */ 631 632 if (!(sc->sc_poll_ih = 633 tx_intr_establish( 634 tc, MAKEINTR(5, TX39_INTRSTATUS5_ALARMINT), 635 IST_EDGE, level, tx39_poll_intr, sc))) { 636 printf("tx39_poll_establish: can't hook\n"); 637 638 splx(s); 639 return 0; 640 } 641 } 642 643 sc->sc_polling++; 644 p->p_desc = sc->sc_polling; 645 TAILQ_INSERT_TAIL(&sc->sc_p_head, p, p_link); 646 ret = (void*)p->p_desc; 647 648 splx(s); 649 return ret; 650 } 651 652 void 653 tx39_poll_disestablish(tc, arg) 654 tx_chipset_tag_t tc; 655 void *arg; 656 { 657 struct tx39icu_softc *sc; 658 struct txpoll_entry *p; 659 int s, desc; 660 661 s = splhigh(); 662 sc = tc->tc_intrt; 663 664 desc = (int)arg; 665 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 666 if (p->p_desc == desc) { 667 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 668 free(p, M_DEVBUF); 669 break; 670 } 671 } 672 673 if (TAILQ_EMPTY(&sc->sc_p_head)) { 674 sc->sc_polling = 0; 675 tx_intr_disestablish(tc, sc->sc_poll_ih); 676 } 677 678 splx(s); 679 return; 680 } 681 682 int 683 tx39_poll_intr(arg) 684 void *arg; 685 { 686 struct tx39icu_softc *sc = arg; 687 struct txpoll_entry *p; 688 689 tx39clock_alarm_refill(sc->sc_tc); 690 691 if (!sc->sc_polling) { 692 return 0; 693 } 694 sc->sc_pollcnt++; 695 TAILQ_FOREACH(p, &sc->sc_p_head, p_link) { 696 if (sc->sc_pollcnt % p->p_cnt == 0) { 697 if ((*p->p_fun)(p->p_arg) == POLL_END) 698 goto disestablish; 699 } 700 } 701 702 return 0; 703 704 disestablish: 705 TAILQ_REMOVE(&sc->sc_p_head, p, p_link); 706 free(p, M_DEVBUF); 707 if (TAILQ_EMPTY(&sc->sc_p_head)) { 708 sc->sc_polling = 0; 709 tx_intr_disestablish(sc->sc_tc, sc->sc_poll_ih); 710 } 711 712 return 0; 713 } 714 #endif /* USE_POLL */ 715 716 void 717 tx39_intr_dump(sc) 718 struct tx39icu_softc *sc; 719 { 720 tx_chipset_tag_t tc = sc->sc_tc; 721 int i, j, ofs; 722 txreg_t reg; 723 char msg[16]; 724 725 for (i = 1; i <= TX39_INTRSET_MAX; i++) { 726 #ifdef TX392X 727 if (i == 6) 728 continue; 729 #endif /* TX392X */ 730 for (reg = j = 0; j < 32; j++) { 731 if (tx39_irqhigh(i, j)) { 732 reg |= (1 << j); 733 } 734 } 735 sprintf(msg, "%d high", i); 736 __bitdisp(reg, 32, 0, msg, 1); 737 sprintf(msg, "%d status", i); 738 __bitdisp(sc->sc_regs[i], 0, 31, msg, 1); 739 ofs = TX39_INTRENABLE_REG(i); 740 reg = tx_conf_read(tc, ofs); 741 sprintf(msg, "%d enable", i); 742 __bitdisp(reg, 0, 31, msg, 1); 743 } 744 reg = sc->sc_regs[0]; 745 printf("<%s><%s> vector=%2d\t\t[6 status]\n", 746 reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--", 747 reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--", 748 TX39_INTRSTATUS6_INTVECT(reg)); 749 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 750 __bitdisp(reg, 0, 18, "6 enable", 1); 751 752 } 753
Indexes created Sun Nov 02 07:10:05 GMT 2025