tx39sibreg.h revision 1.1
1 /* $NetBSD: tx39sibreg.h,v 1.1 2000/01/08 21:07:03 uch Exp $ */ 2 3 /* 4 * Copyright (c) 2000, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* 29 * Toshiba TX3912 SIB module 30 */ 31 32 #define TX39_SIBSIZE_REG 0x060 /* W */ 33 #define TX39_SIBSNDRXSTART_REG 0x064 /* W */ 34 #define TX39_SIBSNDTXSTART_REG 0x068 /* W */ 35 #define TX39_SIBTELRXSTART_REG 0x06c /* W */ 36 #define TX39_SIBTELTXSTART_REG 0x070 /* W */ 37 #define TX39_SIBCTRL_REG 0x074 /* R/W */ 38 #define TX39_SIBSNDHOLD_REG 0x078 /* R/W */ 39 #define TX39_SIBTELHOLD_REG 0x07c /* R/W */ 40 #define TX39_SIBSF0CTRL_REG 0x080 /* R/W */ 41 #define TX39_SIBSF1CTRL_REG 0x084 /* R/W */ 42 #define TX39_SIBSF0STAT_REG 0x088 /* R */ 43 #define TX39_SIBSF1STAT_REG 0x08c /* R */ 44 #define TX39_SIBDMACTRL_REG 0x090 /* R/W */ 45 46 /* 47 * SIB Size Register 48 */ 49 #define TX39_SIBSIZE_SND_SHIFT 18 50 #define TX39_SIBSIZE_TEL_SHIFT 2 51 #define TX39_SIBSIZE_MASK 0xfff 52 53 #define TX39_SIBSIZE_SNDSIZE_SET(val) \ 54 (((((val) >> 2) - 1) << TX39_SIBSIZE_SND_SHIFT) & \ 55 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_SND_SHIFT)) 56 #define TX39_SIBSIZE_TELSIZE_SET(val) \ 57 (((((val) >> 2) - 1) << TX39_SIBSIZE_TEL_SHIFT) & \ 58 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_TEL_SHIFT)) 59 60 /* 61 * SIB Sound RX Start Register 62 * [1:0] reserved 63 */ 64 /* 65 * SIB Sound TX Start Register 66 * [1:0] reserved 67 */ 68 /* 69 * SIB Telecom RX Start Register 70 * [1:0] reserved 71 */ 72 /* 73 * SIB Telecom TX Start Register 74 * [1:0] reserved 75 */ 76 /* 77 * SIB Control Register 78 */ 79 #define TX39_SIBCTRL_SIBIRQ 0x80000000 80 #define TX39_SIBCTRL_ENCNTTEST 0x40000000 /* Don't set */ 81 #define TX39_SIBCTRL_ENDMATEST 0x20000000 /* Don't set */ 82 #define TX39_SIBCTRL_SNDMONO 0x10000000 83 #define TX39_SIBCTRL_RMONOSNDIN 0x08000000 84 85 #define TX39_SIBCTRL_SCLKDIV_SHIFT 24 86 #define TX39_SIBCTRL_SCLKDIV_MASK 0x7 87 #define TX39_SIBCTRL_SCLKDIV(cr) \ 88 (((cr) >> TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 89 TX39_SIBCTRL_SCLKDIV_MASK) 90 #define TX39_SIBCTRL_SCLKDIV_SET(cr, val) \ 91 ((cr) | (((val) << TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 92 (TX39_SIBCTRL_SCLKDIV_MASK << TX39_SIBCTRL_SCLKDIV_SHIFT))) 93 94 #define TX39_SIBCTRL_TEL16 0x00800000 95 96 #define TX39_SIBCTRL_TELFSDIV_SHIFT 16 97 #define TX39_SIBCTRL_TELFSDIV_MASK 0x7f 98 #define TX39_SIBCTRL_TELFSDIV(cr) \ 99 (((cr) >> TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 100 TX39_SIBCTRL_TELFSDIV_MASK) 101 #define TX39_SIBCTRL_TELFSDIV_SET(cr, val) \ 102 ((cr) | (((val) << TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 103 (TX39_SIBCTRL_TELFSDIV_MASK << TX39_SIBCTRL_TELFSDIV_SHIFT))) 104 105 #define TX39_SIBCTRL_SND16 0x00008000 106 107 #define TX39_SIBCTRL_SNDFSDIV_SHIFT 8 108 #define TX39_SIBCTRL_SNDFSDIV_MASK 0x7f 109 #define TX39_SIBCTRL_SNDFSDIV(cr) \ 110 (((cr) >> TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 111 TX39_SIBCTRL_SNDFSDIV_MASK) 112 #define TX39_SIBCTRL_SNDFSDIV_SET(cr, val) \ 113 ((cr) | (((val) << TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 114 (TX39_SIBCTRL_SNDFSDIV_MASK << TX39_SIBCTRL_SNDFSDIV_SHIFT))) 115 116 #define TX39_SIBCTRL_SELTELSF1 0x00000080 117 #define TX39_SIBCTRL_SELSNDSF1 0x00000040 118 #define TX39_SIBCTRL_ENTEL 0x00000020 119 #define TX39_SIBCTRL_ENSND 0x00000010 120 #define TX39_SIBCTRL_SIBLOOP 0x00000008 121 #define TX39_SIBCTRL_ENSF1 0x00000004 122 #define TX39_SIBCTRL_ENSF0 0x00000002 123 #define TX39_SIBCTRL_ENSIB 0x00000001 124 125 /* 126 * SIB Sound RX/TX Holding Register 127 */ 128 /* 129 * SIB Telecom RX/TX Holding Register 130 */ 131 132 /* 133 * SIB Subframe 0 Control Register 134 * SIB Subframe 0 Status Register 135 */ 136 /* Control/Status bit, field definition (See also UCB1200) */ 137 #define TX39_SIBSF0_REGADDR_SHIFT 27 138 #define TX39_SIBSF0_REGADDR_MASK 0xf 139 #define TX39_SIBSF0_REGADDR(cr) \ 140 (((cr) >> TX39_SIBSF0_REGADDR_SHIFT) & \ 141 TX39_SIBSF0_REGADDR_MASK) 142 #define TX39_SIBSF0_REGADDR_SET(cr, val) \ 143 ((cr) | (((val) << TX39_SIBSF0_REGADDR_SHIFT) & \ 144 (TX39_SIBSF0_REGADDR_MASK << TX39_SIBSF0_REGADDR_SHIFT))) 145 146 #define TX39_SIBSF0_WRITE 0x04000000 147 #define TX39_SIBSF0_SNDVALID 0x00020000 148 #define TX39_SIBSF0_TELVALID 0x00010000 149 150 #define TX39_SIBSF0_REGDATA_SHIFT 0 151 #define TX39_SIBSF0_REGDATA_MASK 0xffff 152 #define TX39_SIBSF0_REGDATA(cr) \ 153 (((cr) >> TX39_SIBSF0_REGDATA_SHIFT) & \ 154 TX39_SIBSF0_REGDATA_MASK) 155 #define TX39_SIBSF0_REGDATA_SET(cr, val) \ 156 ((cr) | (((val) << TX39_SIBSF0_REGDATA_SHIFT) & \ 157 (TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT))) 158 #define TX39_SIBSF0_REGDATA_CLR(cr) \ 159 ((cr) &= ~(TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT)) 160 161 /* 162 * SIB Subframe 1 Control Register 163 */ 164 #define TX39_SIBSF1CTRL_MUTE 0x04000000 165 #define TX39_SIBSF1CTRL_MUXL 0x02000000 166 #define TX39_SIBSF1CTRL_MUXR 0x01000000 167 168 #define TX39_SIBSF1CTRL_ADCGAINL_SHIFT 20 169 #define TX39_SIBSF1CTRL_ADCGAINL_MASK 0xf 170 #define TX39_SIBSF1CTRL_ADCGAINL_SET(cr, val) \ 171 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINL_SHIFT) & \ 172 (TX39_SIBSF1CTRL_ADCGAINL_MASK << TX39_SIBSF1CTRL_ADCGAINL_SHIFT))) 173 174 #define TX39_SIBSF1CTRL_ADCGAINR_SHIFT 16 175 #define TX39_SIBSF1CTRL_ADCGAINR_MASK 0xf 176 #define TX39_SIBSF1CTRL_ADCGAINR_SET(cr, val) \ 177 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINR_SHIFT) & \ 178 (TX39_SIBSF1CTRL_ADCGAINR_MASK << TX39_SIBSF1CTRL_ADCGAINR_SHIFT))) 179 180 #define TX39_SIBSF1CTRL_DACATTNL_SHIFT 8 181 #define TX39_SIBSF1CTRL_DACATTNL_MASK 0xf 182 #define TX39_SIBSF1CTRL_DACATTNL_SET(cr, val) \ 183 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNL_SHIFT) & \ 184 (TX39_SIBSF1CTRL_DACATTNL_MASK << TX39_SIBSF1CTRL_DACATTNL_SHIFT))) 185 186 #define TX39_SIBSF1CTRL_DACATTNR_SHIFT 4 187 #define TX39_SIBSF1CTRL_DACATTNR_MASK 0xf 188 #define TX39_SIBSF1CTRL_DACATTNR_SET(cr, val) \ 189 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNR_SHIFT) & \ 190 (TX39_SIBSF1CTRL_DACATTNR_MASK << TX39_SIBSF1CTRL_DACATTNR_SHIFT))) 191 192 #define TX39_SIBSF1CTRL_DIGITALOUT_SHIFT 0 193 #define TX39_SIBSF1CTRL_DIGITALOUT_MASK 0xf 194 #define TX39_SIBSF1CTRL_DIGITALOUT_SET(cr, val) \ 195 ((cr) | (((val) << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT) & \ 196 (TX39_SIBSF1CTRL_DIGITALOUT_MASK << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT))) 197 198 /* 199 * SIB Subframe 1 Status Register 200 */ 201 #define TX39_SIBSF1STAT_ADCVALID 0x04000000 202 #define TX39_SIBSF1STAT_ADCCLIPL 0x02000000 203 #define TX39_SIBSF1STAT_ADCCLIPR 0x01000000 204 205 #define TX39_SIBSF1STAT_ERROR_SHIFT 20 206 #define TX39_SIBSF1STAT_ERROR_MASK 0xf 207 #define TX39_SIBSF1STAT_ERROR_SET(cr, val) \ 208 ((cr) | (((val) << TX39_SIBSF1STAT_ERROR_SHIFT) & \ 209 (TX39_SIBSF1STAT_ERROR_MASK << TX39_SIBSF1STAT_ERROR_SHIFT))) 210 211 #define TX39_SIBSF1STAT_REVISION_SHIFT 16 212 #define TX39_SIBSF1STAT_REVISION_MASK 0xf 213 #define TX39_SIBSF1STAT_REVISION_SET(cr, val) \ 214 ((cr) | (((val) << TX39_SIBSF1STAT_REVISION_SHIFT) & \ 215 (TX39_SIBSF1STAT_REVISION_MASK << TX39_SIBSF1STAT_REVISION_SHIFT))) 216 217 #define TX39_SIBSF1STAT_DIGITALIN_SHIFT 0 218 #define TX39_SIBSF1STAT_DIGITALIN_MASK 0xf 219 #define TX39_SIBSF1STAT_DIGITALIN_SET(cr, val) \ 220 ((cr) | (((val) << TX39_SIBSF1STAT_DIGITALIN_SHIFT) & \ 221 (TX39_SIBSF1STAT_DIGITALIN_MASK << TX39_SIBSF1STAT_DIGITALIN_SHIFT))) 222 223 /* 224 * SIB DMA Control Register 225 */ 226 #define TX39_SIBDMACTRL_SNDBUFF1TIME 0x80000000 227 #define TX39_SIBDMACTRL_SNDDMALOOP 0x40000000 228 229 #define TX39_SIBDMACTRL_SNDDMAPTR_SHIFT 18 230 #define TX39_SIBDMACTRL_SNDDMAPTR_MASK 0xfff 231 #define TX39_SIBDMACTRL_SNDDMAPTR(cr) \ 232 (((cr) >> TX39_SIBDMACTRL_SNDDMAPTR_SHIFT) & \ 233 TX39_SIBDMACTRL_SNDDMAPTR_MASK) 234 235 #define TX39_SIBDMACTRL_ENDMARXSND 0x00020000 236 #define TX39_SIBDMACTRL_ENDMATXSND 0x00010000 237 #define TX39_SIBDMACTRL_TELBUFF1TIME 0x00008000 238 #define TX39_SIBDMACTRL_TELDMALOOP 0x00004000 239 240 #define TX39_SIBDMACTRL_TELDMAPTR_SHIFT 2 241 #define TX39_SIBDMACTRL_TELDMAPTR_MASK 0xfff 242 #define TX39_SIBDMACTRL_TELDMAPTR(cr) \ 243 (((cr) >> TX39_SIBDMACTRL_TELDMAPTR_SHIFT) & \ 244 TX39_SIBDMACTRL_TELDMAPTR_MASK) 245 246 #define TX39_SIBDMACTRL_ENDMARXTEL 0x00000002 247 #define TX39_SIBDMACTRL_ENDMATXTEL 0x00000001 248 249
Indexes created Sun Nov 02 07:10:05 GMT 2025