tx39sibreg.h revision 1.2
1 /* $NetBSD: tx39sibreg.h,v 1.2 2000/03/03 19:54:37 uch Exp $ */ 2 3 /* 4 * Copyright (c) 2000, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* 29 * Toshiba TX3912 SIB module 30 */ 31 32 #define TX39_SIBSIZE_REG 0x060 /* W */ 33 #define TX39_SIBSNDRXSTART_REG 0x064 /* W */ 34 #define TX39_SIBSNDTXSTART_REG 0x068 /* W */ 35 #define TX39_SIBTELRXSTART_REG 0x06c /* W */ 36 #define TX39_SIBTELTXSTART_REG 0x070 /* W */ 37 #define TX39_SIBCTRL_REG 0x074 /* R/W */ 38 #define TX39_SIBSNDHOLD_REG 0x078 /* R/W */ 39 #define TX39_SIBTELHOLD_REG 0x07c /* R/W */ 40 #define TX39_SIBSF0CTRL_REG 0x080 /* R/W */ 41 #define TX39_SIBSF1CTRL_REG 0x084 /* R/W */ 42 #define TX39_SIBSF0STAT_REG 0x088 /* R */ 43 #define TX39_SIBSF1STAT_REG 0x08c /* R */ 44 #define TX39_SIBDMACTRL_REG 0x090 /* R/W */ 45 46 /* 47 * SIB DMA 48 */ 49 #define TX39_SIBDMA_SIZE 16384 50 51 /* 52 * SIB Size Register 53 */ 54 #define TX39_SIBSIZE_SND_SHIFT 18 55 #define TX39_SIBSIZE_TEL_SHIFT 2 56 #define TX39_SIBSIZE_MASK 0xfff 57 58 #define TX39_SIBSIZE_SNDSIZE_SET(cr, val) \ 59 ((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_SND_SHIFT) & \ 60 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_SND_SHIFT))) 61 #define TX39_SIBSIZE_TELSIZE_SET(cr, val) \ 62 ((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_TEL_SHIFT) & \ 63 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_TEL_SHIFT))) 64 65 /* 66 * SIB Sound RX Start Register 67 * [1:0] reserved 68 */ 69 /* 70 * SIB Sound TX Start Register 71 * [1:0] reserved 72 */ 73 /* 74 * SIB Telecom RX Start Register 75 * [1:0] reserved 76 */ 77 /* 78 * SIB Telecom TX Start Register 79 * [1:0] reserved 80 */ 81 /* 82 * SIB Control Register 83 */ 84 #define TX39_SIBCTRL_SIBIRQ 0x80000000 85 #define TX39_SIBCTRL_ENCNTTEST 0x40000000 /* Don't set */ 86 #define TX39_SIBCTRL_ENDMATEST 0x20000000 /* Don't set */ 87 #define TX39_SIBCTRL_SNDMONO 0x10000000 88 #define TX39_SIBCTRL_RMONOSNDIN 0x08000000 89 90 #define TX39_SIBCTRL_SCLKDIV_SHIFT 24 91 #define TX39_SIBCTRL_SCLKDIV_MASK 0x7 92 #define TX39_SIBCTRL_SCLKDIV(cr) \ 93 (((cr) >> TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 94 TX39_SIBCTRL_SCLKDIV_MASK) 95 #define TX39_SIBCTRL_SCLKDIV_SET(cr, val) \ 96 ((cr) | (((val) << TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 97 (TX39_SIBCTRL_SCLKDIV_MASK << TX39_SIBCTRL_SCLKDIV_SHIFT))) 98 99 #define TX39_SIBCTRL_TEL16 0x00800000 100 101 #define TX39_SIBCTRL_TELFSDIV_SHIFT 16 102 #define TX39_SIBCTRL_TELFSDIV_MASK 0x7f 103 #define TX39_SIBCTRL_TELFSDIV(cr) \ 104 (((cr) >> TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 105 TX39_SIBCTRL_TELFSDIV_MASK) 106 #define TX39_SIBCTRL_TELFSDIV_SET(cr, val) \ 107 ((cr) | (((val) << TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 108 (TX39_SIBCTRL_TELFSDIV_MASK << TX39_SIBCTRL_TELFSDIV_SHIFT))) 109 110 #define TX39_SIBCTRL_SND16 0x00008000 111 112 #define TX39_SIBCTRL_SNDFSDIV_SHIFT 8 113 #define TX39_SIBCTRL_SNDFSDIV_MASK 0x7f 114 #define TX39_SIBCTRL_SNDFSDIV(cr) \ 115 (((cr) >> TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 116 TX39_SIBCTRL_SNDFSDIV_MASK) 117 #define TX39_SIBCTRL_SNDFSDIV_SET(cr, val) \ 118 ((cr) | (((val) << TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 119 (TX39_SIBCTRL_SNDFSDIV_MASK << TX39_SIBCTRL_SNDFSDIV_SHIFT))) 120 121 #define TX39_SIBCTRL_SELTELSF1 0x00000080 122 #define TX39_SIBCTRL_SELSNDSF1 0x00000040 123 #define TX39_SIBCTRL_ENTEL 0x00000020 124 #define TX39_SIBCTRL_ENSND 0x00000010 125 #define TX39_SIBCTRL_SIBLOOP 0x00000008 126 #define TX39_SIBCTRL_ENSF1 0x00000004 127 #define TX39_SIBCTRL_ENSF0 0x00000002 128 #define TX39_SIBCTRL_ENSIB 0x00000001 129 130 /* 131 * SIB Sound RX/TX Holding Register 132 */ 133 /* 134 * SIB Telecom RX/TX Holding Register 135 */ 136 137 /* 138 * SIB Subframe 0 Control Register 139 * SIB Subframe 0 Status Register 140 */ 141 /* Control/Status bit, field definition (See also UCB1200) */ 142 #define TX39_SIBSF0_REGADDR_SHIFT 27 143 #define TX39_SIBSF0_REGADDR_MASK 0xf 144 #define TX39_SIBSF0_REGADDR(cr) \ 145 (((cr) >> TX39_SIBSF0_REGADDR_SHIFT) & \ 146 TX39_SIBSF0_REGADDR_MASK) 147 #define TX39_SIBSF0_REGADDR_SET(cr, val) \ 148 ((cr) | (((val) << TX39_SIBSF0_REGADDR_SHIFT) & \ 149 (TX39_SIBSF0_REGADDR_MASK << TX39_SIBSF0_REGADDR_SHIFT))) 150 151 #define TX39_SIBSF0_WRITE 0x04000000 152 #define TX39_SIBSF0_SNDVALID 0x00020000 153 #define TX39_SIBSF0_TELVALID 0x00010000 154 155 #define TX39_SIBSF0_REGDATA_SHIFT 0 156 #define TX39_SIBSF0_REGDATA_MASK 0xffff 157 #define TX39_SIBSF0_REGDATA(cr) \ 158 (((cr) >> TX39_SIBSF0_REGDATA_SHIFT) & \ 159 TX39_SIBSF0_REGDATA_MASK) 160 #define TX39_SIBSF0_REGDATA_SET(cr, val) \ 161 ((cr) | (((val) << TX39_SIBSF0_REGDATA_SHIFT) & \ 162 (TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT))) 163 #define TX39_SIBSF0_REGDATA_CLR(cr) \ 164 ((cr) &= ~(TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT)) 165 166 /* 167 * SIB Subframe 1 Control Register 168 */ 169 #define TX39_SIBSF1CTRL_MUTE 0x04000000 170 #define TX39_SIBSF1CTRL_MUXL 0x02000000 171 #define TX39_SIBSF1CTRL_MUXR 0x01000000 172 173 #define TX39_SIBSF1CTRL_ADCGAINL_SHIFT 20 174 #define TX39_SIBSF1CTRL_ADCGAINL_MASK 0xf 175 #define TX39_SIBSF1CTRL_ADCGAINL_SET(cr, val) \ 176 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINL_SHIFT) & \ 177 (TX39_SIBSF1CTRL_ADCGAINL_MASK << TX39_SIBSF1CTRL_ADCGAINL_SHIFT))) 178 179 #define TX39_SIBSF1CTRL_ADCGAINR_SHIFT 16 180 #define TX39_SIBSF1CTRL_ADCGAINR_MASK 0xf 181 #define TX39_SIBSF1CTRL_ADCGAINR_SET(cr, val) \ 182 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINR_SHIFT) & \ 183 (TX39_SIBSF1CTRL_ADCGAINR_MASK << TX39_SIBSF1CTRL_ADCGAINR_SHIFT))) 184 185 #define TX39_SIBSF1CTRL_DACATTNL_SHIFT 8 186 #define TX39_SIBSF1CTRL_DACATTNL_MASK 0xf 187 #define TX39_SIBSF1CTRL_DACATTNL_SET(cr, val) \ 188 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNL_SHIFT) & \ 189 (TX39_SIBSF1CTRL_DACATTNL_MASK << TX39_SIBSF1CTRL_DACATTNL_SHIFT))) 190 191 #define TX39_SIBSF1CTRL_DACATTNR_SHIFT 4 192 #define TX39_SIBSF1CTRL_DACATTNR_MASK 0xf 193 #define TX39_SIBSF1CTRL_DACATTNR_SET(cr, val) \ 194 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNR_SHIFT) & \ 195 (TX39_SIBSF1CTRL_DACATTNR_MASK << TX39_SIBSF1CTRL_DACATTNR_SHIFT))) 196 197 #define TX39_SIBSF1CTRL_DIGITALOUT_SHIFT 0 198 #define TX39_SIBSF1CTRL_DIGITALOUT_MASK 0xf 199 #define TX39_SIBSF1CTRL_DIGITALOUT_SET(cr, val) \ 200 ((cr) | (((val) << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT) & \ 201 (TX39_SIBSF1CTRL_DIGITALOUT_MASK << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT))) 202 203 /* 204 * SIB Subframe 1 Status Register 205 */ 206 #define TX39_SIBSF1STAT_ADCVALID 0x04000000 207 #define TX39_SIBSF1STAT_ADCCLIPL 0x02000000 208 #define TX39_SIBSF1STAT_ADCCLIPR 0x01000000 209 210 #define TX39_SIBSF1STAT_ERROR_SHIFT 20 211 #define TX39_SIBSF1STAT_ERROR_MASK 0xf 212 #define TX39_SIBSF1STAT_ERROR_SET(cr, val) \ 213 ((cr) | (((val) << TX39_SIBSF1STAT_ERROR_SHIFT) & \ 214 (TX39_SIBSF1STAT_ERROR_MASK << TX39_SIBSF1STAT_ERROR_SHIFT))) 215 216 #define TX39_SIBSF1STAT_REVISION_SHIFT 16 217 #define TX39_SIBSF1STAT_REVISION_MASK 0xf 218 #define TX39_SIBSF1STAT_REVISION_SET(cr, val) \ 219 ((cr) | (((val) << TX39_SIBSF1STAT_REVISION_SHIFT) & \ 220 (TX39_SIBSF1STAT_REVISION_MASK << TX39_SIBSF1STAT_REVISION_SHIFT))) 221 222 #define TX39_SIBSF1STAT_DIGITALIN_SHIFT 0 223 #define TX39_SIBSF1STAT_DIGITALIN_MASK 0xf 224 #define TX39_SIBSF1STAT_DIGITALIN_SET(cr, val) \ 225 ((cr) | (((val) << TX39_SIBSF1STAT_DIGITALIN_SHIFT) & \ 226 (TX39_SIBSF1STAT_DIGITALIN_MASK << TX39_SIBSF1STAT_DIGITALIN_SHIFT))) 227 228 /* 229 * SIB DMA Control Register 230 */ 231 #define TX39_SIBDMACTRL_SNDBUFF1TIME 0x80000000 232 #define TX39_SIBDMACTRL_SNDDMALOOP 0x40000000 233 234 #define TX39_SIBDMACTRL_SNDDMAPTR_SHIFT 18 235 #define TX39_SIBDMACTRL_SNDDMAPTR_MASK 0xfff 236 #define TX39_SIBDMACTRL_SNDDMAPTR(cr) \ 237 (((cr) >> TX39_SIBDMACTRL_SNDDMAPTR_SHIFT) & \ 238 TX39_SIBDMACTRL_SNDDMAPTR_MASK) 239 240 #define TX39_SIBDMACTRL_ENDMARXSND 0x00020000 241 #define TX39_SIBDMACTRL_ENDMATXSND 0x00010000 242 #define TX39_SIBDMACTRL_TELBUFF1TIME 0x00008000 243 #define TX39_SIBDMACTRL_TELDMALOOP 0x00004000 244 245 #define TX39_SIBDMACTRL_TELDMAPTR_SHIFT 2 246 #define TX39_SIBDMACTRL_TELDMAPTR_MASK 0xfff 247 #define TX39_SIBDMACTRL_TELDMAPTR(cr) \ 248 (((cr) >> TX39_SIBDMACTRL_TELDMAPTR_SHIFT) & \ 249 TX39_SIBDMACTRL_TELDMAPTR_MASK) 250 251 #define TX39_SIBDMACTRL_ENDMARXTEL 0x00000002 252 #define TX39_SIBDMACTRL_ENDMATXTEL 0x00000001 253 254
Indexes created Sun Nov 02 07:10:05 GMT 2025