tx39sibreg.h revision 1.3
1 /* $NetBSD: tx39sibreg.h,v 1.3 2001/06/14 11:09:56 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 /* 39 * Toshiba TX3912 SIB module 40 */ 41 42 #define TX39_SIBSIZE_REG 0x060 /* W */ 43 #define TX39_SIBSNDRXSTART_REG 0x064 /* W */ 44 #define TX39_SIBSNDTXSTART_REG 0x068 /* W */ 45 #define TX39_SIBTELRXSTART_REG 0x06c /* W */ 46 #define TX39_SIBTELTXSTART_REG 0x070 /* W */ 47 #define TX39_SIBCTRL_REG 0x074 /* R/W */ 48 #define TX39_SIBSNDHOLD_REG 0x078 /* R/W */ 49 #define TX39_SIBTELHOLD_REG 0x07c /* R/W */ 50 #define TX39_SIBSF0CTRL_REG 0x080 /* R/W */ 51 #define TX39_SIBSF1CTRL_REG 0x084 /* R/W */ 52 #define TX39_SIBSF0STAT_REG 0x088 /* R */ 53 #define TX39_SIBSF1STAT_REG 0x08c /* R */ 54 #define TX39_SIBDMACTRL_REG 0x090 /* R/W */ 55 56 /* 57 * SIB DMA 58 */ 59 #define TX39_SIBDMA_SIZE 16384 60 61 /* 62 * SIB Size Register 63 */ 64 #define TX39_SIBSIZE_SND_SHIFT 18 65 #define TX39_SIBSIZE_TEL_SHIFT 2 66 #define TX39_SIBSIZE_MASK 0xfff 67 68 #define TX39_SIBSIZE_SNDSIZE_SET(cr, val) \ 69 ((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_SND_SHIFT) & \ 70 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_SND_SHIFT))) 71 #define TX39_SIBSIZE_TELSIZE_SET(cr, val) \ 72 ((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_TEL_SHIFT) & \ 73 (TX39_SIBSIZE_MASK << TX39_SIBSIZE_TEL_SHIFT))) 74 75 /* 76 * SIB Sound RX Start Register 77 * [1:0] reserved 78 */ 79 /* 80 * SIB Sound TX Start Register 81 * [1:0] reserved 82 */ 83 /* 84 * SIB Telecom RX Start Register 85 * [1:0] reserved 86 */ 87 /* 88 * SIB Telecom TX Start Register 89 * [1:0] reserved 90 */ 91 /* 92 * SIB Control Register 93 */ 94 #define TX39_SIBCTRL_SIBIRQ 0x80000000 95 #define TX39_SIBCTRL_ENCNTTEST 0x40000000 /* Don't set */ 96 #define TX39_SIBCTRL_ENDMATEST 0x20000000 /* Don't set */ 97 #define TX39_SIBCTRL_SNDMONO 0x10000000 98 #define TX39_SIBCTRL_RMONOSNDIN 0x08000000 99 100 #define TX39_SIBCTRL_SCLKDIV_SHIFT 24 101 #define TX39_SIBCTRL_SCLKDIV_MASK 0x7 102 #define TX39_SIBCTRL_SCLKDIV(cr) \ 103 (((cr) >> TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 104 TX39_SIBCTRL_SCLKDIV_MASK) 105 #define TX39_SIBCTRL_SCLKDIV_SET(cr, val) \ 106 ((cr) | (((val) << TX39_SIBCTRL_SCLKDIV_SHIFT) & \ 107 (TX39_SIBCTRL_SCLKDIV_MASK << TX39_SIBCTRL_SCLKDIV_SHIFT))) 108 109 #define TX39_SIBCTRL_TEL16 0x00800000 110 111 #define TX39_SIBCTRL_TELFSDIV_SHIFT 16 112 #define TX39_SIBCTRL_TELFSDIV_MASK 0x7f 113 #define TX39_SIBCTRL_TELFSDIV(cr) \ 114 (((cr) >> TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 115 TX39_SIBCTRL_TELFSDIV_MASK) 116 #define TX39_SIBCTRL_TELFSDIV_SET(cr, val) \ 117 ((cr) | (((val) << TX39_SIBCTRL_TELFSDIV_SHIFT) & \ 118 (TX39_SIBCTRL_TELFSDIV_MASK << TX39_SIBCTRL_TELFSDIV_SHIFT))) 119 120 #define TX39_SIBCTRL_SND16 0x00008000 121 122 #define TX39_SIBCTRL_SNDFSDIV_SHIFT 8 123 #define TX39_SIBCTRL_SNDFSDIV_MASK 0x7f 124 #define TX39_SIBCTRL_SNDFSDIV(cr) \ 125 (((cr) >> TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 126 TX39_SIBCTRL_SNDFSDIV_MASK) 127 #define TX39_SIBCTRL_SNDFSDIV_SET(cr, val) \ 128 ((cr) | (((val) << TX39_SIBCTRL_SNDFSDIV_SHIFT) & \ 129 (TX39_SIBCTRL_SNDFSDIV_MASK << TX39_SIBCTRL_SNDFSDIV_SHIFT))) 130 131 #define TX39_SIBCTRL_SELTELSF1 0x00000080 132 #define TX39_SIBCTRL_SELSNDSF1 0x00000040 133 #define TX39_SIBCTRL_ENTEL 0x00000020 134 #define TX39_SIBCTRL_ENSND 0x00000010 135 #define TX39_SIBCTRL_SIBLOOP 0x00000008 136 #define TX39_SIBCTRL_ENSF1 0x00000004 137 #define TX39_SIBCTRL_ENSF0 0x00000002 138 #define TX39_SIBCTRL_ENSIB 0x00000001 139 140 /* 141 * SIB Sound RX/TX Holding Register 142 */ 143 /* 144 * SIB Telecom RX/TX Holding Register 145 */ 146 147 /* 148 * SIB Subframe 0 Control Register 149 * SIB Subframe 0 Status Register 150 */ 151 /* Control/Status bit, field definition (See also UCB1200) */ 152 #define TX39_SIBSF0_REGADDR_SHIFT 27 153 #define TX39_SIBSF0_REGADDR_MASK 0xf 154 #define TX39_SIBSF0_REGADDR(cr) \ 155 (((cr) >> TX39_SIBSF0_REGADDR_SHIFT) & \ 156 TX39_SIBSF0_REGADDR_MASK) 157 #define TX39_SIBSF0_REGADDR_SET(cr, val) \ 158 ((cr) | (((val) << TX39_SIBSF0_REGADDR_SHIFT) & \ 159 (TX39_SIBSF0_REGADDR_MASK << TX39_SIBSF0_REGADDR_SHIFT))) 160 161 #define TX39_SIBSF0_WRITE 0x04000000 162 #define TX39_SIBSF0_SNDVALID 0x00020000 163 #define TX39_SIBSF0_TELVALID 0x00010000 164 165 #define TX39_SIBSF0_REGDATA_SHIFT 0 166 #define TX39_SIBSF0_REGDATA_MASK 0xffff 167 #define TX39_SIBSF0_REGDATA(cr) \ 168 (((cr) >> TX39_SIBSF0_REGDATA_SHIFT) & \ 169 TX39_SIBSF0_REGDATA_MASK) 170 #define TX39_SIBSF0_REGDATA_SET(cr, val) \ 171 ((cr) | (((val) << TX39_SIBSF0_REGDATA_SHIFT) & \ 172 (TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT))) 173 #define TX39_SIBSF0_REGDATA_CLR(cr) \ 174 ((cr) &= ~(TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT)) 175 176 /* 177 * SIB Subframe 1 Control Register 178 */ 179 #define TX39_SIBSF1CTRL_MUTE 0x04000000 180 #define TX39_SIBSF1CTRL_MUXL 0x02000000 181 #define TX39_SIBSF1CTRL_MUXR 0x01000000 182 183 #define TX39_SIBSF1CTRL_ADCGAINL_SHIFT 20 184 #define TX39_SIBSF1CTRL_ADCGAINL_MASK 0xf 185 #define TX39_SIBSF1CTRL_ADCGAINL_SET(cr, val) \ 186 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINL_SHIFT) & \ 187 (TX39_SIBSF1CTRL_ADCGAINL_MASK << TX39_SIBSF1CTRL_ADCGAINL_SHIFT))) 188 189 #define TX39_SIBSF1CTRL_ADCGAINR_SHIFT 16 190 #define TX39_SIBSF1CTRL_ADCGAINR_MASK 0xf 191 #define TX39_SIBSF1CTRL_ADCGAINR_SET(cr, val) \ 192 ((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINR_SHIFT) & \ 193 (TX39_SIBSF1CTRL_ADCGAINR_MASK << TX39_SIBSF1CTRL_ADCGAINR_SHIFT))) 194 195 #define TX39_SIBSF1CTRL_DACATTNL_SHIFT 8 196 #define TX39_SIBSF1CTRL_DACATTNL_MASK 0xf 197 #define TX39_SIBSF1CTRL_DACATTNL_SET(cr, val) \ 198 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNL_SHIFT) & \ 199 (TX39_SIBSF1CTRL_DACATTNL_MASK << TX39_SIBSF1CTRL_DACATTNL_SHIFT))) 200 201 #define TX39_SIBSF1CTRL_DACATTNR_SHIFT 4 202 #define TX39_SIBSF1CTRL_DACATTNR_MASK 0xf 203 #define TX39_SIBSF1CTRL_DACATTNR_SET(cr, val) \ 204 ((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNR_SHIFT) & \ 205 (TX39_SIBSF1CTRL_DACATTNR_MASK << TX39_SIBSF1CTRL_DACATTNR_SHIFT))) 206 207 #define TX39_SIBSF1CTRL_DIGITALOUT_SHIFT 0 208 #define TX39_SIBSF1CTRL_DIGITALOUT_MASK 0xf 209 #define TX39_SIBSF1CTRL_DIGITALOUT_SET(cr, val) \ 210 ((cr) | (((val) << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT) & \ 211 (TX39_SIBSF1CTRL_DIGITALOUT_MASK << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT))) 212 213 /* 214 * SIB Subframe 1 Status Register 215 */ 216 #define TX39_SIBSF1STAT_ADCVALID 0x04000000 217 #define TX39_SIBSF1STAT_ADCCLIPL 0x02000000 218 #define TX39_SIBSF1STAT_ADCCLIPR 0x01000000 219 220 #define TX39_SIBSF1STAT_ERROR_SHIFT 20 221 #define TX39_SIBSF1STAT_ERROR_MASK 0xf 222 #define TX39_SIBSF1STAT_ERROR_SET(cr, val) \ 223 ((cr) | (((val) << TX39_SIBSF1STAT_ERROR_SHIFT) & \ 224 (TX39_SIBSF1STAT_ERROR_MASK << TX39_SIBSF1STAT_ERROR_SHIFT))) 225 226 #define TX39_SIBSF1STAT_REVISION_SHIFT 16 227 #define TX39_SIBSF1STAT_REVISION_MASK 0xf 228 #define TX39_SIBSF1STAT_REVISION_SET(cr, val) \ 229 ((cr) | (((val) << TX39_SIBSF1STAT_REVISION_SHIFT) & \ 230 (TX39_SIBSF1STAT_REVISION_MASK << TX39_SIBSF1STAT_REVISION_SHIFT))) 231 232 #define TX39_SIBSF1STAT_DIGITALIN_SHIFT 0 233 #define TX39_SIBSF1STAT_DIGITALIN_MASK 0xf 234 #define TX39_SIBSF1STAT_DIGITALIN_SET(cr, val) \ 235 ((cr) | (((val) << TX39_SIBSF1STAT_DIGITALIN_SHIFT) & \ 236 (TX39_SIBSF1STAT_DIGITALIN_MASK << TX39_SIBSF1STAT_DIGITALIN_SHIFT))) 237 238 /* 239 * SIB DMA Control Register 240 */ 241 #define TX39_SIBDMACTRL_SNDBUFF1TIME 0x80000000 242 #define TX39_SIBDMACTRL_SNDDMALOOP 0x40000000 243 244 #define TX39_SIBDMACTRL_SNDDMAPTR_SHIFT 18 245 #define TX39_SIBDMACTRL_SNDDMAPTR_MASK 0xfff 246 #define TX39_SIBDMACTRL_SNDDMAPTR(cr) \ 247 (((cr) >> TX39_SIBDMACTRL_SNDDMAPTR_SHIFT) & \ 248 TX39_SIBDMACTRL_SNDDMAPTR_MASK) 249 250 #define TX39_SIBDMACTRL_ENDMARXSND 0x00020000 251 #define TX39_SIBDMACTRL_ENDMATXSND 0x00010000 252 #define TX39_SIBDMACTRL_TELBUFF1TIME 0x00008000 253 #define TX39_SIBDMACTRL_TELDMALOOP 0x00004000 254 255 #define TX39_SIBDMACTRL_TELDMAPTR_SHIFT 2 256 #define TX39_SIBDMACTRL_TELDMAPTR_MASK 0xfff 257 #define TX39_SIBDMACTRL_TELDMAPTR(cr) \ 258 (((cr) >> TX39_SIBDMACTRL_TELDMAPTR_SHIFT) & \ 259 TX39_SIBDMACTRL_TELDMAPTR_MASK) 260 261 #define TX39_SIBDMACTRL_ENDMARXTEL 0x00000002 262 #define TX39_SIBDMACTRL_ENDMATXTEL 0x00000001 263 264
Indexes created Sun Nov 02 07:10:05 GMT 2025