gcscide.c revision 1.4
1/* $NetBSD: gcscide.c,v 1.4 2007/06/28 10:22:52 xtraeme Exp $ */ 2 3/* 4 * Copyright (c) 2007 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to the NetBSD Foundation 8 * by Juan Romero Pardines. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Juan Romero Pardines 21 * for the NetBSD Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Driver for the IDE Controller of the National Semiconductor/AMD 41 * CS5535 Companion device. Available on systems with an AMD Geode GX2 42 * CPU, for example the decTOP. 43 * 44 * Datasheet at: 45 * 46 * http://www.amd.com/files/connectivitysolutions/geode/geode_gx/31506_cs5535_databook.pdf 47 */ 48 49#include <sys/cdefs.h> 50__KERNEL_RCSID(0, "$NetBSD: gcscide.c,v 1.4 2007/06/28 10:22:52 xtraeme Exp $"); 51 52#include <sys/param.h> 53#include <sys/systm.h> 54 55#include <dev/pci/pcivar.h> 56#include <dev/pci/pcidevs.h> 57#include <dev/pci/pciidereg.h> 58#include <dev/pci/pciidevar.h> 59 60#include <machine/cpufunc.h> 61 62#define GCSCIDE_MSR_ATAC_BASE 0x51300000 63#define GCSCIDE_ATAC_GLD_MSR_CAP (GCSCIDE_MSR_ATAC_BASE + 0) 64#define GCSCIDE_ATAC_GLD_MSR_CONFIG (GCSCIDE_MSR_ATAC_BASE + 0x01) 65#define GCSCIDE_ATAC_GLD_MSR_SMI (GCSCIDE_MSR_ATAC_BASE + 0x02) 66#define GCSCIDE_ATAC_GLD_MSR_ERROR (GCSCIDE_MSR_ATAC_BASE + 0x03) 67#define GCSCIDE_ATAC_GLD_MSR_PM (GCSCIDE_MSR_ATAC_BASE + 0x04) 68#define GCSCIDE_ATAC_GLD_MSR_DIAG (GCSCIDE_MSR_ATAC_BASE + 0x05) 69#define GCSCIDE_ATAC_IO_BAR (GCSCIDE_MSR_ATAC_BASE + 0x08) 70#define GCSCIDE_ATAC_RESET (GCSCIDE_MSR_ATAC_BASE + 0x10) 71#define GCSCIDE_ATAC_CH0D0_PIO (GCSCIDE_MSR_ATAC_BASE + 0x20) 72#define GCSCIDE_ATAC_CH0D0_DMA (GCSCIDE_MSR_ATAC_BASE + 0x21) 73#define GCSCIDE_ATAC_CH0D1_PIO (GCSCIDE_MSR_ATAC_BASE + 0x22) 74#define GCSCIDE_ATAC_CH0D1_DMA (GCSCIDE_MSR_ATAC_BASE + 0x23) 75#define GCSCIDE_ATAC_PCI_ABRTERR (GCSCIDE_MSR_ATAC_BASE + 0x24) 76#define GCSCIDE_ATAC_BM0_CMD_PRIM 0x00 77#define GCSCIDE_ATAC_BM0_STS_PRIM 0x02 78#define GCSCIDE_ATAC_BM0_PRD 0x04 79#define GCSCIDE_PIO_FORMAT 0x80000000UL 80 81static int gcscide_match(struct device *, struct cfdata *, void *); 82static void gcscide_attach(struct device *, struct device *, void *); 83 84static void gcscide_chip_map(struct pciide_softc *, struct pci_attach_args *); 85static void gcscide_setup_channel(struct ata_channel *); 86 87/* PIO Format 1 timings */ 88static const uint32_t gcscide_pio_timings[] = { 89 0xf7f4f7f4, /* PIO Mode 0 */ 90 0x53f3f173, /* PIO Mode 1 */ 91 0x13f18141, /* PIO Mode 2 */ 92 0x51315131, /* PIO Mode 3 */ 93 0x11311131 /* PIO Mode 4 */ 94}; 95 96static const uint32_t gcscide_mdma_timings[] = { 97 0x7f0ffff3, /* MDMA Mode 0 */ 98 0x7f035352, /* MDMA Mode 1 */ 99 0x7f024241 /* MDMA Mode 2 */ 100}; 101 102static const uint32_t gcscide_udma_timings[] = { 103 0x7f7436a1, /* Ultra DMA Mode 0 */ 104 0x7f733481, /* Ultra DMA Mode 1 */ 105 0x7f723261, /* Ultra DMA Mode 2 */ 106 0x7f713161, /* Ultra DMA Mode 3 */ 107 0x7f703061 /* Ultra DMA Mode 4 */ 108}; 109 110CFATTACH_DECL(gcscide, sizeof(struct pciide_softc), 111 gcscide_match, gcscide_attach, NULL, NULL); 112 113static const struct pciide_product_desc pciide_gcscide_products[] = { 114 { 115 PCI_PRODUCT_NS_CS5535_IDE, 116 0, 117 "National Semiconductor/AMD CS5535 IDE Controller", 118 gcscide_chip_map 119 }, 120 { 0, 0, NULL, NULL } 121}; 122 123static int 124gcscide_match(struct device *parent, struct cfdata *cfdata, void *aux) 125{ 126 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 127 128 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 129 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 130 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 131 pciide_lookup_product(pa->pa_id, pciide_gcscide_products)) 132 return 2; 133 return 0; 134} 135 136static void 137gcscide_attach(struct device *parent, struct device *self, void *aux) 138{ 139 struct pci_attach_args *pa = aux; 140 struct pciide_softc *sc = (struct pciide_softc *)self; 141 142 pciide_common_attach(sc, pa, 143 pciide_lookup_product(pa->pa_id, pciide_gcscide_products)); 144} 145 146static void 147gcscide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 148{ 149 pcireg_t interface; 150 bus_size_t cmdsize, ctlsize; 151 152 if (pciide_chipen(sc, pa) == 0) 153 return; 154 155 aprint_verbose("%s: bus-master DMA support present", 156 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 157 pciide_mapreg_dma(sc, pa); 158 aprint_verbose("\n"); 159 160 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 161 if (sc->sc_dma_ok) { 162 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 163 sc->sc_wdcdev.irqack = pciide_irqack; 164 } 165 166 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 167 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 168 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 169 sc->sc_wdcdev.sc_atac.atac_set_modes = gcscide_setup_channel; 170 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 171 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 172 173 interface = PCI_INTERFACE(pa->pa_class); 174 175 wdc_allocate_regs(&sc->sc_wdcdev); 176 177 if (pciide_chansetup(sc, 0, interface) == 0) 178 return; 179 180 pciide_mapchan(pa, &sc->pciide_channels[0], interface, 181 &cmdsize, &ctlsize, pciide_pci_intr); 182} 183 184static void 185gcscide_setup_channel(struct ata_channel *chp) 186{ 187 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 188 struct ata_drive_datas *drvp; 189 uint64_t reg = 0; 190 int drive, s; 191 192 pciide_channel_dma_setup(cp); 193 194 for (drive = 0; drive < 2; drive++) { 195 drvp = &chp->ch_drive[drive]; 196 if ((drvp->drive_flags & DRIVE) == 0) 197 continue; 198 if ((drvp->drive_flags & DRIVE_UDMA) || 199 (drvp->drive_flags & DRIVE_DMA)) { 200 reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 201 GCSCIDE_ATAC_CH0D0_DMA); 202 /* Preserve PIO Format bit */ 203 reg &= ~GCSCIDE_PIO_FORMAT; 204 } 205 206 if (drvp->drive_flags & DRIVE_UDMA) { 207 s = splbio(); 208 drvp->drive_flags &= ~DRIVE_DMA; 209 splx(s); 210 /* Set UDMA and MDMA timings */ 211 reg |= gcscide_udma_timings[drvp->UDMA_mode]; 212 reg |= gcscide_mdma_timings[drvp->DMA_mode]; 213 214 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 215 GCSCIDE_ATAC_CH0D0_DMA, reg); 216 217 } else if (drvp->drive_flags & DRIVE_DMA) { 218 /* 219 * Disable Ultra DMA and set a MDMA mode. 220 */ 221 if (reg & gcscide_udma_timings[drvp->UDMA_mode]) 222 reg &= ~gcscide_udma_timings[drvp->UDMA_mode]; 223 224 reg |= gcscide_mdma_timings[drvp->DMA_mode]; 225 226 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 227 GCSCIDE_ATAC_CH0D0_DMA, reg); 228 } else { 229 /* 230 * Set PIO Format 1 timings. 231 */ 232 reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 233 GCSCIDE_ATAC_CH0D0_DMA); 234 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 235 GCSCIDE_ATAC_CH0D0_DMA, reg | GCSCIDE_PIO_FORMAT); 236 } 237 /* Set PIO mode and timing */ 238 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_PIO : GCSCIDE_ATAC_CH0D0_PIO, 239 gcscide_pio_timings[drvp->PIO_mode]); 240 } 241} 242