gcscide.c revision 1.8
1/* $NetBSD: gcscide.c,v 1.8 2010/11/05 18:07:23 jakllsch Exp $ */ 2 3/*- 4 * Copyright (c) 2007 Juan Romero Pardines. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28/* 29 * Driver for the IDE Controller of the National Semiconductor/AMD 30 * CS5535 Companion device. Available on systems with an AMD Geode GX2 31 * CPU, for example the decTOP. 32 * 33 * Datasheet at: 34 * 35 * http://www.amd.com/files/connectivitysolutions/geode/geode_gx/31506_cs5535_databook.pdf 36 */ 37 38#include <sys/cdefs.h> 39__KERNEL_RCSID(0, "$NetBSD: gcscide.c,v 1.8 2010/11/05 18:07:23 jakllsch Exp $"); 40 41#include <sys/param.h> 42#include <sys/systm.h> 43 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcidevs.h> 46#include <dev/pci/pciidereg.h> 47#include <dev/pci/pciidevar.h> 48 49#include <machine/cpufunc.h> 50 51/* 52 * 6.4 - ATA-5 Controller Register Definitions. 53 */ 54#define GCSCIDE_MSR_ATAC_BASE 0x51300000 55#define GCSCIDE_ATAC_GLD_MSR_CAP (GCSCIDE_MSR_ATAC_BASE + 0) 56#define GCSCIDE_ATAC_GLD_MSR_CONFIG (GCSCIDE_MSR_ATAC_BASE + 0x01) 57#define GCSCIDE_ATAC_GLD_MSR_SMI (GCSCIDE_MSR_ATAC_BASE + 0x02) 58#define GCSCIDE_ATAC_GLD_MSR_ERROR (GCSCIDE_MSR_ATAC_BASE + 0x03) 59#define GCSCIDE_ATAC_GLD_MSR_PM (GCSCIDE_MSR_ATAC_BASE + 0x04) 60#define GCSCIDE_ATAC_GLD_MSR_DIAG (GCSCIDE_MSR_ATAC_BASE + 0x05) 61#define GCSCIDE_ATAC_IO_BAR (GCSCIDE_MSR_ATAC_BASE + 0x08) 62#define GCSCIDE_ATAC_RESET (GCSCIDE_MSR_ATAC_BASE + 0x10) 63#define GCSCIDE_ATAC_CH0D0_PIO (GCSCIDE_MSR_ATAC_BASE + 0x20) 64#define GCSCIDE_ATAC_CH0D0_DMA (GCSCIDE_MSR_ATAC_BASE + 0x21) 65#define GCSCIDE_ATAC_CH0D1_PIO (GCSCIDE_MSR_ATAC_BASE + 0x22) 66#define GCSCIDE_ATAC_CH0D1_DMA (GCSCIDE_MSR_ATAC_BASE + 0x23) 67#define GCSCIDE_ATAC_PCI_ABRTERR (GCSCIDE_MSR_ATAC_BASE + 0x24) 68#define GCSCIDE_ATAC_BM0_CMD_PRIM 0x00 69#define GCSCIDE_ATAC_BM0_STS_PRIM 0x02 70#define GCSCIDE_ATAC_BM0_PRD 0x04 71/* 72 * ATAC_CH0D0_DMA registers: 73 * 74 * PIO Format (bit 31): Format 1 allows independent control of command 75 * and data per drive, while Format 0 selects the slowest speed 76 * of the two drives. 77 */ 78#define GCSCIDE_ATAC_PIO_FORMAT (1 << 31) /* PIO Mode Format 1 */ 79/* 80 * DMA_SEL (bit 20): sets Ultra DMA mode (if enabled) or Multi-word 81 * DMA mode (if disabled). 82 */ 83#define GCSCIDE_ATAC_DMA_SEL (1 << 20) 84 85static int gcscide_match(device_t, cfdata_t, void *); 86static void gcscide_attach(device_t, device_t, void *); 87 88static void gcscide_chip_map(struct pciide_softc *, struct pci_attach_args *); 89static void gcscide_setup_channel(struct ata_channel *); 90 91/* PIO Format 1 settings */ 92static const uint32_t gcscide_pio_timings[] = { 93 0xf7f4f7f4, /* PIO Mode 0 */ 94 0x53f3f173, /* PIO Mode 1 */ 95 0x13f18141, /* PIO Mode 2 */ 96 0x51315131, /* PIO Mode 3 */ 97 0x11311131 /* PIO Mode 4 */ 98}; 99 100static const uint32_t gcscide_mdma_timings[] = { 101 0x7f0ffff3, /* MDMA Mode 0 */ 102 0x7f035352, /* MDMA Mode 1 */ 103 0x7f024241 /* MDMA Mode 2 */ 104}; 105 106static const uint32_t gcscide_udma_timings[] = { 107 0x7f7436a1, /* Ultra DMA Mode 0 */ 108 0x7f733481, /* Ultra DMA Mode 1 */ 109 0x7f723261, /* Ultra DMA Mode 2 */ 110 0x7f713161, /* Ultra DMA Mode 3 */ 111 0x7f703061 /* Ultra DMA Mode 4 */ 112}; 113 114CFATTACH_DECL_NEW(gcscide, sizeof(struct pciide_softc), 115 gcscide_match, gcscide_attach, NULL, NULL); 116 117static const struct pciide_product_desc pciide_gcscide_products[] = { 118 { 119 PCI_PRODUCT_NS_CS5535_IDE, 120 0, 121 "National Semiconductor/AMD CS5535 IDE Controller", 122 gcscide_chip_map 123 }, 124 { 0, 0, NULL, NULL } 125}; 126 127static int 128gcscide_match(device_t parent, cfdata_t cfdata, void *aux) 129{ 130 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 131 132 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 133 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 134 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 135 pciide_lookup_product(pa->pa_id, pciide_gcscide_products)) 136 return 2; 137 return 0; 138} 139 140static void 141gcscide_attach(device_t parent, device_t self, void *aux) 142{ 143 struct pci_attach_args *pa = aux; 144 struct pciide_softc *sc = device_private(self); 145 146 sc->sc_wdcdev.sc_atac.atac_dev = self; 147 148 pciide_common_attach(sc, pa, 149 pciide_lookup_product(pa->pa_id, pciide_gcscide_products)); 150} 151 152static void 153gcscide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 154{ 155 pcireg_t interface; 156 157 if (pciide_chipen(sc, pa) == 0) 158 return; 159 160 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 161 "bus-master DMA support present"); 162 pciide_mapreg_dma(sc, pa); 163 aprint_verbose("\n"); 164 165 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 166 if (sc->sc_dma_ok) { 167 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 168 sc->sc_wdcdev.irqack = pciide_irqack; 169 } 170 171 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 172 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 173 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 174 sc->sc_wdcdev.sc_atac.atac_set_modes = gcscide_setup_channel; 175 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 176 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 177 178 interface = PCI_INTERFACE(pa->pa_class); 179 180 wdc_allocate_regs(&sc->sc_wdcdev); 181 182 if (pciide_chansetup(sc, 0, interface) == 0) 183 return; 184 185 pciide_mapchan(pa, &sc->pciide_channels[0], interface, 186 pciide_pci_intr); 187} 188 189static void 190gcscide_setup_channel(struct ata_channel *chp) 191{ 192 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 193 struct ata_drive_datas *drvp; 194 uint64_t reg = 0; 195 int drive, s; 196 197 pciide_channel_dma_setup(cp); 198 199 for (drive = 0; drive < 2; drive++) { 200 drvp = &chp->ch_drive[drive]; 201 if ((drvp->drive_flags & DRIVE) == 0) 202 continue; 203 204 reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 205 GCSCIDE_ATAC_CH0D0_DMA); 206 207 if (drvp->drive_flags & DRIVE_UDMA) { 208 s = splbio(); 209 drvp->drive_flags &= ~DRIVE_DMA; 210 splx(s); 211 /* Enable the Ultra DMA mode bit */ 212 reg |= GCSCIDE_ATAC_DMA_SEL; 213 /* set the Ultra DMA mode */ 214 reg |= gcscide_udma_timings[drvp->UDMA_mode]; 215 216 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 217 GCSCIDE_ATAC_CH0D0_DMA, reg); 218 219 } else if (drvp->drive_flags & DRIVE_DMA) { 220 /* Enable the Multi-word DMA bit */ 221 reg &= ~GCSCIDE_ATAC_DMA_SEL; 222 /* set the Multi-word DMA mode */ 223 reg |= gcscide_mdma_timings[drvp->DMA_mode]; 224 225 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 226 GCSCIDE_ATAC_CH0D0_DMA, reg); 227 } 228 229 /* Always use PIO Format 1. */ 230 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 231 GCSCIDE_ATAC_CH0D0_DMA, reg | GCSCIDE_ATAC_PIO_FORMAT); 232 233 /* Set PIO mode */ 234 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_PIO : GCSCIDE_ATAC_CH0D0_PIO, 235 gcscide_pio_timings[drvp->PIO_mode]); 236 } 237} 238