opti82c558reg.h revision 1.1.10.2
1 1.1.10.2 bouyer /* $NetBSD: opti82c558reg.h,v 1.1.10.2 2000/11/20 20:09:34 bouyer Exp $ */ 2 1.1.10.2 bouyer 3 1.1.10.2 bouyer /* 4 1.1.10.2 bouyer * Copyright (c) 1999, by UCHIYAMA Yasushi 5 1.1.10.2 bouyer * All rights reserved. 6 1.1.10.2 bouyer * 7 1.1.10.2 bouyer * Redistribution and use in source and binary forms, with or without 8 1.1.10.2 bouyer * modification, are permitted provided that the following conditions 9 1.1.10.2 bouyer * are met: 10 1.1.10.2 bouyer * 1. Redistributions of source code must retain the above copyright 11 1.1.10.2 bouyer * notice, this list of conditions and the following disclaimer. 12 1.1.10.2 bouyer * 2. The name of the developer may NOT be used to endorse or promote products 13 1.1.10.2 bouyer * derived from this software without specific prior written permission. 14 1.1.10.2 bouyer * 15 1.1.10.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 1.1.10.2 bouyer * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 1.1.10.2 bouyer * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 1.1.10.2 bouyer * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 1.1.10.2 bouyer * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 1.1.10.2 bouyer * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 1.1.10.2 bouyer * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1.10.2 bouyer * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 1.1.10.2 bouyer * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 1.1.10.2 bouyer * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 1.1.10.2 bouyer * SUCH DAMAGE. 26 1.1.10.2 bouyer */ 27 1.1.10.2 bouyer 28 1.1.10.2 bouyer /* 29 1.1.10.2 bouyer * Register definitions for the Opti 82c558 PCI-ISA bridge interrupt 30 1.1.10.2 bouyer * controller. 31 1.1.10.2 bouyer */ 32 1.1.10.2 bouyer 33 1.1.10.2 bouyer /* 34 1.1.10.2 bouyer * PCI IRQ Select Register 35 1.1.10.2 bouyer */ 36 1.1.10.2 bouyer 37 1.1.10.2 bouyer #define VIPER_CFG_PIRQ 0x40 /* PCI configuration space */ 38 1.1.10.2 bouyer 39 1.1.10.2 bouyer /* 40 1.1.10.2 bouyer * Trigger setting: 41 1.1.10.2 bouyer * 42 1.1.10.2 bouyer * [1:7]=>5,9,10,11,12,14,15 Edge = 0 Level = 1 43 1.1.10.2 bouyer */ 44 1.1.10.2 bouyer #define VIPER_CFG_TRIGGER_SHIFT 16 45 1.1.10.2 bouyer 46 1.1.10.2 bouyer #define VIPER_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) 47 1.1.10.2 bouyer 48 1.1.10.2 bouyer #define VIPER_PIRQ_MASK 0xde20 49 1.1.10.2 bouyer #define VIPER_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ 50 1.1.10.2 bouyer ((1 << (irq)) & VIPER_PIRQ_MASK) != 0) 51 1.1.10.2 bouyer 52 1.1.10.2 bouyer #define VIPER_PIRQ_NONE 0 53 1.1.10.2 bouyer #define VIPER_PIRQ_5 1 54 1.1.10.2 bouyer #define VIPER_PIRQ_9 2 55 1.1.10.2 bouyer #define VIPER_PIRQ_10 3 56 1.1.10.2 bouyer #define VIPER_PIRQ_11 4 57 1.1.10.2 bouyer #define VIPER_PIRQ_12 5 58 1.1.10.2 bouyer #define VIPER_PIRQ_14 6 59 1.1.10.2 bouyer #define VIPER_PIRQ_15 7 60 1.1.10.2 bouyer 61 1.1.10.2 bouyer #define VIPER_PIRQ_SELECT_MASK 0x07 62 1.1.10.2 bouyer #define VIPER_PIRQ_SELECT_SHIFT 3 63 1.1.10.2 bouyer 64 1.1.10.2 bouyer #define VIPER_PIRQ(reg, x) (((reg) >> ((x) * VIPER_PIRQ_SELECT_SHIFT)) \ 65 1.1.10.2 bouyer & VIPER_PIRQ_SELECT_MASK) 66
Indexes created Sun Nov 02 07:10:05 GMT 2025