piixreg.h revision 1.1.10.2
1 1.1.10.2 bouyer /* $NetBSD: piixreg.h,v 1.1.10.2 2000/11/20 20:09:35 bouyer Exp $ */ 2 1.1.10.2 bouyer 3 1.1.10.2 bouyer /* 4 1.1.10.2 bouyer * Copyright (c) 1999, by UCHIYAMA Yasushi 5 1.1.10.2 bouyer * All rights reserved. 6 1.1.10.2 bouyer * 7 1.1.10.2 bouyer * Redistribution and use in source and binary forms, with or without 8 1.1.10.2 bouyer * modification, are permitted provided that the following conditions 9 1.1.10.2 bouyer * are met: 10 1.1.10.2 bouyer * 1. Redistributions of source code must retain the above copyright 11 1.1.10.2 bouyer * notice, this list of conditions and the following disclaimer. 12 1.1.10.2 bouyer * 2. The name of the developer may NOT be used to endorse or promote products 13 1.1.10.2 bouyer * derived from this software without specific prior written permission. 14 1.1.10.2 bouyer * 15 1.1.10.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 1.1.10.2 bouyer * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 1.1.10.2 bouyer * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 1.1.10.2 bouyer * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 1.1.10.2 bouyer * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 1.1.10.2 bouyer * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 1.1.10.2 bouyer * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1.10.2 bouyer * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 1.1.10.2 bouyer * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 1.1.10.2 bouyer * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 1.1.10.2 bouyer * SUCH DAMAGE. 26 1.1.10.2 bouyer */ 27 1.1.10.2 bouyer 28 1.1.10.2 bouyer /* 29 1.1.10.2 bouyer * Register definitions for the Intel PIIX PCI-ISA bridge interrupt controller. 30 1.1.10.2 bouyer */ 31 1.1.10.2 bouyer 32 1.1.10.2 bouyer /* 33 1.1.10.2 bouyer * PIRQ[3:0]# - PIRQ ROUTE CONTROL REGISTERS 34 1.1.10.2 bouyer * 35 1.1.10.2 bouyer * PCI Configuration registers 0x60, 0x61, 0x62, 0x63 36 1.1.10.2 bouyer */ 37 1.1.10.2 bouyer 38 1.1.10.2 bouyer #define PIIX_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) 39 1.1.10.2 bouyer 40 1.1.10.2 bouyer #define PIIX_PIRQ_MASK 0xdef8 41 1.1.10.2 bouyer #define PIIX_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ 42 1.1.10.2 bouyer ((1 << (irq)) & PIIX_PIRQ_MASK) != 0) 43 1.1.10.2 bouyer 44 1.1.10.2 bouyer #define PIIX_CFG_PIRQ 0x60 /* PCI configuration space */ 45 1.1.10.2 bouyer #define PIIX_CFG_PIRQ_NONE 0x80 46 1.1.10.2 bouyer #define PIIX_CFG_PIRQ_MASK 0x0f 47 1.1.10.2 bouyer #define PIIX_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff) 48 1.1.10.2 bouyer 49 1.1.10.2 bouyer /* 50 1.1.10.2 bouyer * ELCR - EDGE/LEVEL CONTROL REGISTER 51 1.1.10.2 bouyer * 52 1.1.10.2 bouyer * PCI I/O registers 0x4d0, 0x4d1 53 1.1.10.2 bouyer */ 54 1.1.10.2 bouyer #define PIIX_REG_ELCR 0x4d0 55 1.1.10.2 bouyer #define PIIX_REG_ELCR_SIZE 2 56
Indexes created Sat Nov 01 21:09:44 GMT 2025