if_mcreg.h revision 1.1
1/*- 2 * Copyright (c) 1997 David Huang <khym@bga.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the author may not be used to endorse or promote products 11 * derived from this software without specific prior written permission 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 */ 25 26/* 27 * AMD MACE (Am79C940) register definitions 28 */ 29#define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */ 30#define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */ 31#define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */ 32#define MACE_XMTFS 3 /* Transmit Frame Status (read only) */ 33#define MACE_XMTRC 4 /* Transmit Retry Count (read only) */ 34#define MACE_RCVFC 5 /* Receive Frame Control (read/write) */ 35#define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */ 36#define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */ 37#define MACE_IR 8 /* Interrupt Register (read only) */ 38#define MACE_IMR 9 /* Interrupt Mask Register (read/write) */ 39#define MACE_PR 10 /* Poll Register (read only) */ 40#define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */ 41#define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */ 42#define MACE_MACCC 13 /* MAC Configuration Control (read/write) */ 43#define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */ 44#define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */ 45#define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */ 46#define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */ 47#define MACE_IAC 18 /* Internal Address Configuration (read/write) */ 48/* RESERVED 19 Reserved (read/write as 0) */ 49#define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */ 50#define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */ 51/* RESERVED 22 Reserved (read/write as 0) */ 52/* RESERVED 23 Reserved (read/write as 0) */ 53#define MACE_MPC 24 /* Missed Packet Count (read only) */ 54/* RESERVED 25 Reserved (read/write as 0) */ 55#define MACE_RNTPC 26 /* Runt Packet Count (read only) */ 56#define MACE_RCVCC 27 /* Receive Collision Count (read only) */ 57/* RESERVED 28 Reserved (read/write as 0) */ 58#define MACE_UTR 29 /* User Test Register (read/write) */ 59#define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */ 60#define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */ 61 62#define MACE_NREGS 32 63 64/* 2: Transmit Frame Control (XMTFC) */ 65#define DRTRY 0x80 /* Disable Retry */ 66#define DXMTFCS 0x08 /* Disable Transmit FCS */ 67#define APADXMT 0x01 /* Auto Pad Transmit */ 68 69/* 3: Transmit Frame Status (XMTFS) */ 70#define XMTSV 0x80 /* Transmit Status Valid */ 71#define UFLO 0x40 /* Underflow */ 72#define LCOL 0x20 /* Late Collision */ 73#define MORE 0x10 /* More than one retry needed */ 74#define ONE 0x08 /* Exactly one retry needed */ 75#define DEFER 0x04 /* Transmission deferred */ 76#define LCAR 0x02 /* Loss of Carrier */ 77#define RTRY 0x01 /* Retry Error */ 78 79/* 4: Transmit Retry Count (XMTRC) */ 80#define EXDEF 0x80 /* Excessive Defer */ 81#define XMTRC 0x0f /* Transmit Retry Count */ 82 83/* 5: Receive Frame Control (RCVFC) */ 84#define LLRCV 0x08 /* Low Latency Receive */ 85#define MR 0x04 /* Match/Reject */ 86#define ASTRPRCV 0x01 /* Auto Strip Receive */ 87 88/* 6: Receive Frame Status (RCVFS) */ 89/* 4 byte register; read 4 times to get all of the bytes */ 90/* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */ 91 92/* Read 2: RFS1 - Receive Status (RCVSTS) */ 93#define OFLO 0x80 /* Overflow flag */ 94#define CLSN 0x40 /* Collision flag */ 95#define FRAM 0x20 /* Framing Error flag */ 96#define FCS 0x10 /* FCS Error flag */ 97#define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */ 98 99/* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */ 100 101/* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */ 102 103/* 7: FIFO Frame Count (FIFOFC) */ 104#define RCVFC 0xf0 /* Receive Frame Count */ 105#define XMTFC 0x0f /* Transmit Frame Count */ 106 107/* 8: Interrupt Register (IR) */ 108#define JAB 0x80 /* Jabber Error */ 109#define BABL 0x40 /* Babble Error */ 110#define CERR 0x20 /* Collision Error */ 111#define RCVCCO 0x10 /* Receive Collision Count Overflow */ 112#define RNTPCO 0x08 /* Runt Packet Count Overflow */ 113#define MPCO 0x04 /* Missed Packet Count Overflow */ 114#define RCVINT 0x02 /* Receive Interrupt */ 115#define XMTINT 0x01 /* Transmit Interrupt */ 116 117/* 9: Interrut Mask Register (IMR) */ 118#define JABM 0x80 /* Jabber Error Mask */ 119#define BABLM 0x40 /* Babble Error Mask */ 120#define CERRM 0x20 /* Collision Error Mask */ 121#define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */ 122#define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */ 123#define MPCOM 0x04 /* Missed Packet Count Overflow Mask */ 124#define RCVINTM 0x02 /* Receive Interrupt Mask */ 125#define XMTINTM 0x01 /* Transmit Interrupt Mask */ 126 127/* 10: Poll Register (PR) */ 128#define XMTSV 0x80 /* Transmit Status Valid */ 129#define TDTREQ 0x40 /* Transmit Data Transfer Request */ 130#define RDTREQ 0x20 /* Receive Data Transfer Request */ 131 132/* 11: BIU Configuration Control (BIUCC) */ 133#define BSWP 0x40 /* Byte Swap */ 134#define XMTSP 0x30 /* Transmit Start Point */ 135#define XMTSP_4 0x00 /* 4 bytes */ 136#define XMTSP_16 0x10 /* 16 bytes */ 137#define XMTSP_64 0x20 /* 64 bytes */ 138#define XMTSP_112 0x30 /* 112 bytes */ 139#define SWRST 0x01 /* Software Reset */ 140 141/* 12: FIFO Configuration Control (FIFOCC) */ 142#define XMTFW 0xc0 /* Transmit FIFO Watermark */ 143#define XMTFW_8 0x00 /* 8 write cycles */ 144#define XMTFW_16 0x40 /* 16 write cycles */ 145#define XMTFW_32 0x80 /* 32 write cycles */ 146#define RCVFW 0x30 /* Receive FIFO Watermark */ 147#define RCVFW_16 0x00 /* 16 bytes */ 148#define RCVFW_32 0x10 /* 32 bytes */ 149#define RCVFW_64 0x20 /* 64 bytes */ 150#define XMTFWU 0x08 /* Transmit FIFO Watermark Update */ 151#define RCVFWU 0x04 /* Receive FIFO Watermark Update */ 152#define XMTBRST 0x02 /* Transmit Burst */ 153#define RCVBRST 0x01 /* Receive Burst */ 154 155/* 13: MAC Configuration (MACCC) */ 156#define PROM 0x80 /* Promiscuous */ 157#define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */ 158#define EMBA 0x20 /* Enable Modified Back-off Algorithm */ 159#define DRCVPA 0x08 /* Disable Receive Physical Address */ 160#define DRCVBC 0x04 /* Disable Receive Broadcast */ 161#define ENXMT 0x02 /* Enable Transmit */ 162#define ENRCV 0x01 /* Enable Receive */ 163 164/* 14: PLS Configuration Control (PLSCC) */ 165#define XMTSEL 0x08 /* Transmit Mode Select */ 166#define PORTSEL 0x06 /* Port Select */ 167#define PORTSEL_AUI 0x00 /* Select AUI */ 168#define PORTSEL_10BT 0x02 /* Select 10BASE-T */ 169#define PORTSEL_DAI 0x04 /* Select DAI port */ 170#define PORTSEL_GPSI 0x06 /* Select GPSI */ 171#define ENPLSIO 0x01 /* Enable PLS I/O */ 172 173/* 15: PHY Configuration (PHYCC) */ 174#define LNKFL 0x80 /* Link Fail */ 175#define DLNKTST 0x40 /* Disable Link Test */ 176#define REVPOL 0x20 /* Reversed Polarity */ 177#define DAPC 0x10 /* Disable Auto Polarity Correction */ 178#define LRT 0x08 /* Low Receive Threshold */ 179#define ASEL 0x04 /* Auto Select */ 180#define RWAKE 0x02 /* Remote Wake */ 181#define AWAKE 0x01 /* Auto Wake */ 182 183/* 18: Internal Address Configuration (IAC) */ 184#define ADDRCHG 0x80 /* Address Change */ 185#define PHYADDR 0x04 /* Physical Address Reset */ 186#define LOGADDR 0x02 /* Logical Address Reset */ 187 188/* 28: User Test Register (UTR) */ 189#define RTRE 0x80 /* Reserved Test Register Enable */ 190#define RTRD 0x40 /* Reserved Test Register Disable */ 191#define RPA 0x20 /* Run Packet Accept */ 192#define FCOLL 0x10 /* Force Collision */ 193#define RCVFCSE 0x08 /* Receive FCS Enable */ 194#define LOOP 0x06 /* Loopback Control */ 195#define LOOP_NONE 0x00 /* No Loopback */ 196#define LOOP_EXT 0x02 /* External Loopback */ 197#define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */ 198#define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */ 199