lock.h revision 1.8 
1/*	$NetBSD: lock.h,v 1.8 2005/12/28 19:09:29 perry Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Wayne Knowles.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 *    must display the following acknowledgement:
20 *	This product includes software developed by the NetBSD
21 *	Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 *    contributors may be used to endorse or promote products derived
24 *    from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39/*
40 * Machine-dependent spin lock operations for MIPS R4000 Processors.
41 *
42 * Note:  R3000 doesn't have any atomic update instructions
43 */
44
45#ifndef _MIPS_LOCK_H_
46#define	_MIPS_LOCK_H_
47
48static __inline void
49__cpu_simple_lock_init(__cpu_simple_lock_t *lp)
50{
51
52	__asm volatile(
53		"# -- BEGIN __cpu_simple_lock_init\n"
54		"	.set push		\n"
55		"	.set mips2		\n"
56		"	sw	$0, %0		\n"
57		"	sync			\n"
58		"	.set pop		\n"
59		"# -- END __cpu_simple_lock_init\n"
60		: "=m" (*lp));
61}
62
63static __inline void
64__cpu_simple_lock(__cpu_simple_lock_t *lp)
65{
66	unsigned long t0;
67
68	/*
69	 * Note, if we detect that the lock is held when
70	 * we do the initial load-locked, we spin using
71	 * a non-locked load to save the coherency logic
72	 * some work.
73	 */
74
75	__asm volatile(
76		"# -- BEGIN __cpu_simple_lock	\n"
77		"	.set push		\n"
78		"	.set mips2		\n"
79		"1:	ll	%0, %3		\n"
80		"	bnez	%0, 2f		\n"
81		"	nop	       # BDslot	\n"
82		"	li	%0, %2		\n"
83		"	sc	%0, %1		\n"
84		"	beqz	%0, 1b		\n"
85		"	nop	       # BDslot	\n"
86		"	nop			\n"
87		"	sync			\n"
88		"	j	3f		\n"
89		"	nop			\n"
90		"	nop			\n"
91		"2:	lw	%0, %3		\n"
92		"	bnez	%0, 2b		\n"
93		"	nop	       # BDslot	\n"
94		"	j	1b		\n"
95		"	nop			\n"
96		"3:				\n"
97		"	.set pop		\n"
98		"# -- END __cpu_simple_lock	\n"
99		: "=r" (t0), "+m" (*lp)
100		: "i" (__SIMPLELOCK_LOCKED), "1" (*lp));
101}
102
103static __inline int
104__cpu_simple_lock_try(__cpu_simple_lock_t *lp)
105{
106	unsigned long t0, v0;
107
108	__asm volatile(
109		"# -- BEGIN __cpu_simple_lock_try\n"
110		"	.set push		\n"
111		"	.set mips2		\n"
112		"1:	ll	%0, %4		\n"
113		"	bnez	%0, 2f		\n"
114		"	nop	       # BDslot	\n"
115		"	li	%0, %3		\n"
116		"	sc	%0, %2		\n"
117		"	beqz	%0, 2f		\n"
118		"	nop	       # BDslot	\n"
119		"	li	%1, 1		\n"
120		"	sync			\n"
121		"	j	3f		\n"
122		"	nop			\n"
123		"	nop			\n"
124		"2:	li	%1, 0		\n"
125		"3:				\n"
126		"	.set pop		\n"
127		"# -- END __cpu_simple_lock_try	\n"
128		: "=r" (t0), "=r" (v0), "+m" (*lp)
129		: "i" (__SIMPLELOCK_LOCKED), "2" (*lp));
130
131	return (v0 != 0);
132}
133
134static __inline void
135__cpu_simple_unlock(__cpu_simple_lock_t *lp)
136{
137
138	__asm volatile(
139		"# -- BEGIN __cpu_simple_unlock \n"
140		"	.set push		\n"
141		"	.set mips2		\n"
142		"	sync			\n"
143		"	sw	$0, %0		\n"
144		"	.set pop		\n"
145		"# -- END __cpu_simple_unlock	\n"
146		: "=m" (*lp));
147}
148#endif /* _MIPS_LOCK_H_ */
149