sb1250_pci.h revision 1.1 
1/*  *********************************************************************
2    *  SB1250 Board Support Package
3    *
4    *  PCI constants				File: sb1250_pci.h
5    *
6    *  This module contains constants and macros to describe
7    *  the PCI interface on the SB1250.
8    *
9    *  SB1250 specification level:  User's manual 1/02/02
10    *
11    *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
12    *
13    *********************************************************************
14    *
15    *  Copyright 2000,2001
16    *  Broadcom Corporation. All rights reserved.
17    *
18    *  This software is furnished under license and may be used and
19    *  copied only in accordance with the following terms and
20    *  conditions.  Subject to these conditions, you may download,
21    *  copy, install, use, modify and distribute modified or unmodified
22    *  copies of this software in source and/or binary form.  No title
23    *  or ownership is transferred hereby.
24    *
25    *  1) Any source code used, modified or distributed must reproduce
26    *     and retain this copyright notice and list of conditions as
27    *     they appear in the source file.
28    *
29    *  2) No right is granted to use any trade name, trademark, or
30    *     logo of Broadcom Corporation. Neither the "Broadcom
31    *     Corporation" name nor any trademark or logo of Broadcom
32    *     Corporation may be used to endorse or promote products
33    *     derived from this software without the prior written
34    *     permission of Broadcom Corporation.
35    *
36    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
37    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
38    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
39    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
40    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
41    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
42    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
44    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
45    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
46    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
47    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
48    *     THE POSSIBILITY OF SUCH DAMAGE.
49    ********************************************************************* */
50
51
52#ifndef _SB1250_PCI_H
53#define _SB1250_PCI_H
54
55#include "sb1250_defs.h"
56
57#define K_PCI_VENDOR_SIBYTE	0x166D
58#define K_PCI_DEVICE_SB1250	0x0001
59
60/*
61 * PCI Interface Type 0 configuration header
62 */
63
64#define R_PCI_TYPE0_DEVICEID	0x0000
65#define R_PCI_TYPE0_CMDSTATUS	0x0004
66#define R_PCI_TYPE0_CLASSREV	0x0008
67#define R_PCI_TYPE0_DEVHDR	0x000C
68#define R_PCI_TYPE0_BAR0	0x0010	/* translated via mapping table */
69#define R_PCI_TYPE0_BAR1	0x0014	/* reserved */
70#define R_PCI_TYPE0_BAR2	0x0018	/* mbox 0 */
71#define R_PCI_TYPE0_BAR3	0x001C	/* mbox 1 */
72#define R_PCI_TYPE0_BAR4	0x0020	/* low memory */
73#define R_PCI_TYPE0_BAR5	0x0024	/* high memory */
74#define R_PCI_TYPE0_CARDBUSCIS	0x0028
75#define R_PCI_TYPE0_SUBSYSID	0x002C
76#define R_PCI_TYPE0_ROMBASE	0x0030
77#define R_PCI_TYPE0_CAPPTR	0x0034	/* not used */
78#define R_PCI_TYPE0_RESERVED1	0x0038
79#define R_PCI_TYPE0_INTGRANT	0x003C	/* interrupt pin and grant latency */
80#define R_PCI_TYPE0_TIMEOUT	0x0040	/* FControl, Timeout */
81#define R_PCI_TYPE0_FCONTROL	0x0040	/* FControl, Timeout */
82#define R_PCI_TYPE0_MAPBASE	0x0044	/* 0x44 through 0x80 - map table */
83#define PCI_TYPE0_MAPENTRIES	32	/* 64 bytes, 32 entries */
84#define R_PCI_TYPE0_ERRORADDR	0x0084
85#define R_PCI_TYPE0_ADDSTATUS	0x0088
86#define R_PCI_TYPE0_SUBSYSSET	0x008C	/* only accessible from ZBBus */
87#define R_PCI_TYPE0_READHOST	0x0094	/* Read Host register */		/* PASS2 */
88#define R_PCI_TYPE0_ADXTEND	0x0098	/* Adaptive Extend register */		/* PASS2 */
89
90/*
91 * PCI Device ID register
92 */
93
94#define S_PCI_DEVICEID_VENDOR		0
95#define M_PCI_DEVICEID_VENDOR		_SB_MAKEMASK_32(16,S_PCI_DEVICEID_VENDOR)
96#define V_PCI_DEVICEID_VENDOR(x)	_SB_MAKEVALUE_32(x,S_PCI_DEVICEID_VENDOR)
97#define G_PCI_DEVICEID_VENDOR(x)	_SB_GETVALUE_32(x,S_PCI_DEVICEID_VENDOR,M_PCI_DEVICEID_VENDOR)
98
99#define S_PCI_DEVICEID_DEVICEID		16
100#define M_PCI_DEVICEID_DEVICEID		_SB_MAKEMASK_32(16,S_PCI_DEVICEID_DEVICEID)
101#define V_PCI_DEVICEID_DEVICEID(x)	_SB_MAKEVALUE_32(x,S_PCI_DEVICEID_DEVICEID)
102#define G_PCI_DEVICEID_DEVICEID(x)	_SB_GETVALUE_32(x,S_PCI_DEVICEID_DEVICEID,M_PCI_DEVICEID_DEVICEID)
103
104
105/*
106 * PCI Command Register (Table 8-4)
107 */
108
109#define M_PCI_CMD_IOSPACE_EN		_SB_MAKEMASK1_32(0)
110#define M_PCI_CMD_MEMSPACE_EN		_SB_MAKEMASK1_32(1)
111#define M_PCI_CMD_MASTER_EN		_SB_MAKEMASK1_32(2)
112#define M_PCI_CMD_SPECCYC_EN		_SB_MAKEMASK1_32(3)
113#define M_PCI_CMD_MEMWRINV_EN		_SB_MAKEMASK1_32(4)
114#define M_PCI_CMD_VGAPALSNP_EN		_SB_MAKEMASK1_32(5)
115#define M_PCI_CMD_PARERRRESP		_SB_MAKEMASK1_32(6)
116#define M_PCI_CMD_STEPCTRL		_SB_MAKEMASK1_32(7)
117#define M_PCI_CMD_SERR_EN		_SB_MAKEMASK1_32(8)
118#define M_PCI_CMD_FASTB2B_EN		_SB_MAKEMASK1_32(9)
119
120/*
121 * PCI class and revision registers
122 */
123
124#define S_PCI_CLASSREV_REV		0
125#define M_PCI_CLASSREV_REV		_SB_MAKEMASK_32(8,S_PCI_CLASSREV_REV)
126#define V_PCI_CLASSREV_REV(x)		_SB_MAKEVALUE_32(x,S_PCI_CLASSREV_REV)
127#define G_PCI_CLASSREV_REV(x)		_SB_GETVALUE_32(x,S_PCI_CLASSREV_REV,M_PCI_CLASSREV_REV)
128
129#define S_PCI_CLASSREV_CLASS		8
130#define M_PCI_CLASSREV_CLASS		_SB_MAKEMASK_32(24,S_PCI_CLASSREV_CLASS)
131#define V_PCI_CLASSREV_CLASS(x)		_SB_MAKEVALUE_32(x,S_PCI_CLASSREV_CLASS)
132#define G_PCI_CLASSREV_CLASS(x)		_SB_GETVALUE_32(x,S_PCI_CLASSREV_CLASS,M_PCI_CLASSREV_CLASS)
133
134#define K_PCI_REV			0x01
135#define K_PCI_CLASS			0x060000
136
137/*
138 * Device Header (offset 0x0C)
139 */
140
141#define S_PCI_DEVHDR_CLINESZ		0
142#define M_PCI_DEVHDR_CLINESZ		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
143#define V_PCI_DEVHDR_CLINESZ(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
144#define G_PCI_DEVHDR_CLINESZ(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
145
146#define S_PCI_DEVHDR_LATTMR		8
147#define M_PCI_DEVHDR_LATTMR		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTMR)
148#define V_PCI_DEVHDR_LATTMR(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTMR)
149#define G_PCI_DEVHDR_LATTMR(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTMR,M_PCI_DEVHDR_LATTMR)
150
151#define S_PCI_DEVHDR_HDRTYPE		16
152#define M_PCI_DEVHDR_HDRTYPE		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
153#define V_PCI_DEVHDR_HDRTYPE(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
154#define G_PCI_DEVHDR_HDRTYPE(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
155
156#define K_PCI_DEVHDR_HDRTYPE_TYPE0	0
157
158#define S_PCI_DEVHDR_BIST		24
159#define M_PCI_DEVHDR_BIST		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
160#define V_PCI_DEVHDR_BIST(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
161#define G_PCI_DEVHDR_BIST(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
162
163/*
164 * PCI Status Register (Table 8-5).  Note that these constants
165 * assume you've read the command and status register
166 * together (32-bit read at offset 0x04)
167 */
168
169#define M_PCI_STATUS_CAPLIST		_SB_MAKEMASK1_32(20)
170#define M_PCI_STATUS_66MHZCAP		_SB_MAKEMASK1_32(21)
171#define M_PCI_STATUS_RESERVED2		_SB_MAKEMASK1_32(22)
172#define M_PCI_STATUS_FASTB2BCAP		_SB_MAKEMASK1_32(23)
173#define M_PCI_STATUS_MSTRDPARERR	_SB_MAKEMASK1_32(24)
174
175#define S_PCI_STATUS_DEVSELTIMING	25
176#define M_PCI_STATUS_DEVSELTIMING	_SB_MAKEMASK_32(2,S_PCI_STATUS_DEVSELTIMING)
177#define V_PCI_STATUS_DEVSELTIMING(x)	_SB_MAKEVALUE_32(x,S_PCI_STATUS_DEVSELTIMING)
178#define G_PCI_STATUS_DEVSELTIMING(x)	_SB_GETVALUE_32(x,S_PCI_STATUS_DEVSELTIMING,M_PCI_STATUS_DEVSELTIMING)
179
180#define M_PCI_STATUS_SIGDTGTABORT	_SB_MAKEMASK1_32(27)
181#define M_PCI_STATUS_RCVDTGTABORT	_SB_MAKEMASK1_32(28)
182#define M_PCI_STATUS_RCVDMSTRABORT	_SB_MAKEMASK1_32(29)
183#define M_PCI_STATUS_SIGDSERR		_SB_MAKEMASK1_32(30)
184#define M_PCI_STATUS_DETPARERR		_SB_MAKEMASK1_32(31)
185
186/*
187 * Device Header Register (Table 8-6, Table 8-7)
188 */
189
190#define S_PCI_DEVHDR_CLINESZ		0
191#define M_PCI_DEVHDR_CLINESZ		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
192#define V_PCI_DEVHDR_CLINESZ(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
193#define G_PCI_DEVHDR_CLINESZ(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
194
195#define S_PCI_DEVHDR_LATTIME		8
196#define M_PCI_DEVHDR_LATTIME		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTIME)
197#define V_PCI_DEVHDR_LATTIME(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTIME)
198#define G_PCI_DEVHDR_LATTIME(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTIME,M_PCI_DEVHDR_LATTIME)
199
200#define S_PCI_DEVHDR_HDRTYPE		16
201#define M_PCI_DEVHDR_HDRTYPE		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
202#define V_PCI_DEVHDR_HDRTYPE(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
203#define G_PCI_DEVHDR_HDRTYPE(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
204
205#define S_PCI_DEVHDR_BIST		24
206#define M_PCI_DEVHDR_BIST		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
207#define V_PCI_DEVHDR_BIST(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
208#define G_PCI_DEVHDR_BIST(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
209
210/*
211 * Timeout and feature control Register (Table 8-8) (Table 8-9)
212 * Note that these constants assume you've read the timeout/fcontrol register
213 * together (32-bit read at offset 0x40)
214 */
215
216#define S_PCI_TIMEOUT_TRDY		0
217#define M_PCI_TIMEOUT_TRDY		_SB_MAKEMASK_32(8,S_PCI_TIMEOUT_TRDY)
218#define V_PCI_TIMEOUT_TRDY(x)		_SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_TRDY)
219#define G_PCI_TIMEOUT_TRDY(x)		_SB_GETVALUE_32(x,S_PCI_TIMEOUT_TRDY,M_PCI_TIMEOUT_TRDY)
220
221#define S_PCI_TIMEOUT_RETRY		8
222#define M_PCI_TIMEOUT_RETRY		_SB_MAKEMASK_32(8,S_PCI_TIMEOUT_RETRY)
223#define V_PCI_TIMEOUT_RETRY(x)		_SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_RETRY)
224#define G_PCI_TIMEOUT_RETRY(x)		_SB_GETVALUE_32(x,S_PCI_TIMEOUT_RETRY,M_PCI_TIMEOUT_RETRY)
225
226#define M_PCI_FCONTROL_BAR4_EN		_SB_MAKEMASK1_32(16)
227#define M_PCI_FCONTROL_BAR5_EN		_SB_MAKEMASK1_32(17)
228#define M_PCI_FCONTROL_PTP_EN		_SB_MAKEMASK1_32(18)
229#define M_PCI_FCONTROL_ADAPT_RETRY_EN	_SB_MAKEMASK1_32(19)
230
231#define S_PCI_FCONTROL_MIN_TAR_RETRY	20
232#define M_PCI_FCONTROL_MIN_TAR_RETRY	_SB_MAKEMASK_32(3,S_PCI_FCONTROL_MIN_TAR_RETRY)
233#define V_PCI_FCONTROL_MIN_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY)
234#define G_PCI_FCONTROL_MIN_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY,M_PCI_FCONTROL_MIN_TAR_RETRY)
235
236#define S_PCI_FCONTROL_NOM_TAR_RETRY	23
237#define M_PCI_FCONTROL_NOM_TAR_RETRY	_SB_MAKEMASK_32(4,S_PCI_FCONTROL_NOM_TAR_RETRY)
238#define V_PCI_FCONTROL_NOM_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY)
239#define G_PCI_FCONTROL_NOM_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY,M_PCI_FCONTROL_NOM_TAR_RETRY)
240
241#define S_PCI_FCONTROL_MAX_TAR_RETRY	27
242#define M_PCI_FCONTROL_MAX_TAR_RETRY	_SB_MAKEMASK_32(5,S_PCI_FCONTROL_MAX_TAR_RETRY)
243#define V_PCI_FCONTROL_MAX_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY)
244#define G_PCI_FCONTROL_MAX_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY,M_PCI_FCONTROL_MAX_TAR_RETRY)
245
246/*
247 * BAR0 Map Table Entry (Offsets 0x40-0x80) (Table 8-10)
248 */
249
250#define M_PCI_BAR0MAP_ENABLE		_SB_MAKEMASK1_32(0)
251#define M_PCI_BAR0MAP_SENDLDT		_SB_MAKEMASK1_32(1)
252#define S_PCI_BAR0MAP_ADDR		12
253#define M_PCI_BAR0MAP_ADDR		_SB_MAKEMASK_32(20,S_PCI_BAR0MAP_ADDR)
254
255/*
256 * Additional Status Register (Table 8-11)
257 */
258
259#define M_PCI_ASTATUS_HOTPLUG_EN	_SB_MAKEMASK1_32(0)
260#define M_PCI_ASTATUS_SERR_DET		_SB_MAKEMASK1_32(1)
261#define M_PCI_ASTATUS_TRDYERR		_SB_MAKEMASK1_32(2)
262#define M_PCI_ASTATUS_RETRTYERR		_SB_MAKEMASK1_32(3)
263#define M_PCI_ASTATUS_TRDYINTMASK	_SB_MAKEMASK1_32(4)
264#define M_PCI_ASTATUS_RETRYINTMASK	_SB_MAKEMASK1_32(5)
265#define M_PCI_ASTATUS_SIGNALINTA	_SB_MAKEMASK1_32(6)
266
267/*
268 * Read Host Register  (PASS2)
269 */
270
271#define M_PCI_READHOST_RDHOST	_SB_MAKEMASK1_32(0)		/* PASS2 */
272
273/*
274 * Adaptive Extend Register (PASS2)
275 */
276
277#define S_PCI_ADXTEND_NOM_TAR_RETRY	1
278#define M_PCI_ADXTEND_NOM_TAR_RETRY	_SB_MAKEMASK_32(3,S_PCI_ADXTEND_NOM_TAR_RETRY)
279#define V_PCI_ADXTEND_NOM_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY)
280#define G_PCI_ADXTEND_NOM_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY,M_PCI_ADXTEND_NOM_TAR_RETRY)
281
282#define S_PCI_ADXTEND_MAX_TAR_RETRY	4
283#define M_PCI_ADXTEND_MAX_TAR_RETRY	_SB_MAKEMASK_32(2,S_PCI_ADXTEND_MAX_TAR_RETRY)
284#define V_PCI_ADXTEND_MAX_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY)
285#define G_PCI_ADXTEND_MAX_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY,M_PCI_ADXTEND_MAX_TAR_RETRY)
286
287#define M_PCI_ADXTEND_DIS_DMAR_IOW_DEP  _SB_MAKEMASK1_32(6)
288#define M_PCI_ADXTEND_DIS_MEMRD_BE      _SB_MAKEMASK1_32(6)
289
290
291#endif
292
293
294