sb1250_pci.h revision 1.2 
1/*  *********************************************************************
2    *  SB1250 Board Support Package
3    *
4    *  PCI constants				File: sb1250_pci.h
5    *
6    *  This module contains constants and macros to describe
7    *  the PCI interface on the SB1250.
8    *
9    *  SB1250 specification level:  User's manual 1/02/02
10    *
11    *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
12    *
13    *********************************************************************
14    *
15    *  Copyright 2000,2001
16    *  Broadcom Corporation. All rights reserved.
17    *
18    *  This software is furnished under license and may be used and
19    *  copied only in accordance with the following terms and
20    *  conditions.  Subject to these conditions, you may download,
21    *  copy, install, use, modify and distribute modified or unmodified
22    *  copies of this software in source and/or binary form.  No title
23    *  or ownership is transferred hereby.
24    *
25    *  1) Any source code used, modified or distributed must reproduce
26    *     and retain this copyright notice and list of conditions as
27    *     they appear in the source file.
28    *
29    *  2) No right is granted to use any trade name, trademark, or
30    *     logo of Broadcom Corporation. Neither the "Broadcom
31    *     Corporation" name nor any trademark or logo of Broadcom
32    *     Corporation may be used to endorse or promote products
33    *     derived from this software without the prior written
34    *     permission of Broadcom Corporation.
35    *
36    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
37    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
38    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
39    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
40    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
41    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
42    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
44    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
45    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
46    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
47    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
48    *     THE POSSIBILITY OF SUCH DAMAGE.
49    ********************************************************************* */
50
51
52#ifndef _SB1250_PCI_H
53#define _SB1250_PCI_H
54
55#include "sb1250_defs.h"
56
57#define K_PCI_VENDOR_SIBYTE	0x166D
58#define K_PCI_DEVICE_SB1250	0x0001
59
60/*
61 * PCI Interface Type 0 configuration header
62 */
63
64#define R_PCI_TYPE0_DEVICEID	0x0000
65#define R_PCI_TYPE0_CMDSTATUS	0x0004
66#define R_PCI_TYPE0_CLASSREV	0x0008
67#define R_PCI_TYPE0_DEVHDR	0x000C
68#define R_PCI_TYPE0_BAR0	0x0010	/* translated via mapping table */
69#define R_PCI_TYPE0_BAR1	0x0014	/* reserved */
70#define R_PCI_TYPE0_BAR2	0x0018	/* mbox 0 */
71#define R_PCI_TYPE0_BAR3	0x001C	/* mbox 1 */
72#define R_PCI_TYPE0_BAR4	0x0020	/* low memory */
73#define R_PCI_TYPE0_BAR5	0x0024	/* high memory */
74#define R_PCI_TYPE0_CARDBUSCIS	0x0028
75#define R_PCI_TYPE0_SUBSYSID	0x002C
76#define R_PCI_TYPE0_ROMBASE	0x0030
77#define R_PCI_TYPE0_CAPPTR	0x0034	/* not used */
78#define R_PCI_TYPE0_RESERVED1	0x0038
79#define R_PCI_TYPE0_INTGRANT	0x003C	/* interrupt pin and grant latency */
80#define R_PCI_TYPE0_TIMEOUT	0x0040	/* FControl, Timeout */
81#define R_PCI_TYPE0_FCONTROL	0x0040	/* FControl, Timeout */
82#define R_PCI_TYPE0_MAPBASE	0x0044	/* 0x44 through 0x80 - map table */
83#define PCI_TYPE0_MAPENTRIES	32	/* 64 bytes, 32 entries */
84#define R_PCI_TYPE0_ERRORADDR	0x0084
85#define R_PCI_TYPE0_ADDSTATUS	0x0088
86#define R_PCI_TYPE0_SUBSYSSET	0x008C	/* only accessible from ZBBus */
87#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
88#define R_PCI_TYPE0_READHOST	0x0094	/* Read Host register */
89#define R_PCI_TYPE0_ADXTEND	0x0098	/* Adaptive Extend register */
90#endif /* 1250 PASS2 || 112x PASS1 */
91
92/*
93 * PCI Device ID register
94 */
95
96#define S_PCI_DEVICEID_VENDOR		0
97#define M_PCI_DEVICEID_VENDOR		_SB_MAKEMASK_32(16,S_PCI_DEVICEID_VENDOR)
98#define V_PCI_DEVICEID_VENDOR(x)	_SB_MAKEVALUE_32(x,S_PCI_DEVICEID_VENDOR)
99#define G_PCI_DEVICEID_VENDOR(x)	_SB_GETVALUE_32(x,S_PCI_DEVICEID_VENDOR,M_PCI_DEVICEID_VENDOR)
100
101#define S_PCI_DEVICEID_DEVICEID		16
102#define M_PCI_DEVICEID_DEVICEID		_SB_MAKEMASK_32(16,S_PCI_DEVICEID_DEVICEID)
103#define V_PCI_DEVICEID_DEVICEID(x)	_SB_MAKEVALUE_32(x,S_PCI_DEVICEID_DEVICEID)
104#define G_PCI_DEVICEID_DEVICEID(x)	_SB_GETVALUE_32(x,S_PCI_DEVICEID_DEVICEID,M_PCI_DEVICEID_DEVICEID)
105
106
107/*
108 * PCI Command Register (Table 8-4)
109 */
110
111#define M_PCI_CMD_IOSPACE_EN		_SB_MAKEMASK1_32(0)
112#define M_PCI_CMD_MEMSPACE_EN		_SB_MAKEMASK1_32(1)
113#define M_PCI_CMD_MASTER_EN		_SB_MAKEMASK1_32(2)
114#define M_PCI_CMD_SPECCYC_EN		_SB_MAKEMASK1_32(3)
115#define M_PCI_CMD_MEMWRINV_EN		_SB_MAKEMASK1_32(4)
116#define M_PCI_CMD_VGAPALSNP_EN		_SB_MAKEMASK1_32(5)
117#define M_PCI_CMD_PARERRRESP		_SB_MAKEMASK1_32(6)
118#define M_PCI_CMD_STEPCTRL		_SB_MAKEMASK1_32(7)
119#define M_PCI_CMD_SERR_EN		_SB_MAKEMASK1_32(8)
120#define M_PCI_CMD_FASTB2B_EN		_SB_MAKEMASK1_32(9)
121
122/*
123 * PCI class and revision registers
124 */
125
126#define S_PCI_CLASSREV_REV		0
127#define M_PCI_CLASSREV_REV		_SB_MAKEMASK_32(8,S_PCI_CLASSREV_REV)
128#define V_PCI_CLASSREV_REV(x)		_SB_MAKEVALUE_32(x,S_PCI_CLASSREV_REV)
129#define G_PCI_CLASSREV_REV(x)		_SB_GETVALUE_32(x,S_PCI_CLASSREV_REV,M_PCI_CLASSREV_REV)
130
131#define S_PCI_CLASSREV_CLASS		8
132#define M_PCI_CLASSREV_CLASS		_SB_MAKEMASK_32(24,S_PCI_CLASSREV_CLASS)
133#define V_PCI_CLASSREV_CLASS(x)		_SB_MAKEVALUE_32(x,S_PCI_CLASSREV_CLASS)
134#define G_PCI_CLASSREV_CLASS(x)		_SB_GETVALUE_32(x,S_PCI_CLASSREV_CLASS,M_PCI_CLASSREV_CLASS)
135
136#define K_PCI_REV			0x01
137#define K_PCI_CLASS			0x060000
138
139/*
140 * Device Header (offset 0x0C)
141 */
142
143#define S_PCI_DEVHDR_CLINESZ		0
144#define M_PCI_DEVHDR_CLINESZ		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
145#define V_PCI_DEVHDR_CLINESZ(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
146#define G_PCI_DEVHDR_CLINESZ(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
147
148#define S_PCI_DEVHDR_LATTMR		8
149#define M_PCI_DEVHDR_LATTMR		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTMR)
150#define V_PCI_DEVHDR_LATTMR(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTMR)
151#define G_PCI_DEVHDR_LATTMR(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTMR,M_PCI_DEVHDR_LATTMR)
152
153#define S_PCI_DEVHDR_HDRTYPE		16
154#define M_PCI_DEVHDR_HDRTYPE		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
155#define V_PCI_DEVHDR_HDRTYPE(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
156#define G_PCI_DEVHDR_HDRTYPE(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
157
158#define K_PCI_DEVHDR_HDRTYPE_TYPE0	0
159
160#define S_PCI_DEVHDR_BIST		24
161#define M_PCI_DEVHDR_BIST		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
162#define V_PCI_DEVHDR_BIST(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
163#define G_PCI_DEVHDR_BIST(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
164
165/*
166 * PCI Status Register (Table 8-5).  Note that these constants
167 * assume you've read the command and status register
168 * together (32-bit read at offset 0x04)
169 */
170
171#define M_PCI_STATUS_CAPLIST		_SB_MAKEMASK1_32(20)
172#define M_PCI_STATUS_66MHZCAP		_SB_MAKEMASK1_32(21)
173#define M_PCI_STATUS_RESERVED2		_SB_MAKEMASK1_32(22)
174#define M_PCI_STATUS_FASTB2BCAP		_SB_MAKEMASK1_32(23)
175#define M_PCI_STATUS_MSTRDPARERR	_SB_MAKEMASK1_32(24)
176
177#define S_PCI_STATUS_DEVSELTIMING	25
178#define M_PCI_STATUS_DEVSELTIMING	_SB_MAKEMASK_32(2,S_PCI_STATUS_DEVSELTIMING)
179#define V_PCI_STATUS_DEVSELTIMING(x)	_SB_MAKEVALUE_32(x,S_PCI_STATUS_DEVSELTIMING)
180#define G_PCI_STATUS_DEVSELTIMING(x)	_SB_GETVALUE_32(x,S_PCI_STATUS_DEVSELTIMING,M_PCI_STATUS_DEVSELTIMING)
181
182#define M_PCI_STATUS_SIGDTGTABORT	_SB_MAKEMASK1_32(27)
183#define M_PCI_STATUS_RCVDTGTABORT	_SB_MAKEMASK1_32(28)
184#define M_PCI_STATUS_RCVDMSTRABORT	_SB_MAKEMASK1_32(29)
185#define M_PCI_STATUS_SIGDSERR		_SB_MAKEMASK1_32(30)
186#define M_PCI_STATUS_DETPARERR		_SB_MAKEMASK1_32(31)
187
188/*
189 * Device Header Register (Table 8-6, Table 8-7)
190 */
191
192#define S_PCI_DEVHDR_CLINESZ		0
193#define M_PCI_DEVHDR_CLINESZ		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
194#define V_PCI_DEVHDR_CLINESZ(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
195#define G_PCI_DEVHDR_CLINESZ(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
196
197#define S_PCI_DEVHDR_LATTIME		8
198#define M_PCI_DEVHDR_LATTIME		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTIME)
199#define V_PCI_DEVHDR_LATTIME(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTIME)
200#define G_PCI_DEVHDR_LATTIME(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTIME,M_PCI_DEVHDR_LATTIME)
201
202#define S_PCI_DEVHDR_HDRTYPE		16
203#define M_PCI_DEVHDR_HDRTYPE		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
204#define V_PCI_DEVHDR_HDRTYPE(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
205#define G_PCI_DEVHDR_HDRTYPE(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
206
207#define S_PCI_DEVHDR_BIST		24
208#define M_PCI_DEVHDR_BIST		_SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
209#define V_PCI_DEVHDR_BIST(x)		_SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
210#define G_PCI_DEVHDR_BIST(x)		_SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
211
212/*
213 * Timeout and feature control Register (Table 8-8) (Table 8-9)
214 * Note that these constants assume you've read the timeout/fcontrol register
215 * together (32-bit read at offset 0x40)
216 */
217
218#define S_PCI_TIMEOUT_TRDY		0
219#define M_PCI_TIMEOUT_TRDY		_SB_MAKEMASK_32(8,S_PCI_TIMEOUT_TRDY)
220#define V_PCI_TIMEOUT_TRDY(x)		_SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_TRDY)
221#define G_PCI_TIMEOUT_TRDY(x)		_SB_GETVALUE_32(x,S_PCI_TIMEOUT_TRDY,M_PCI_TIMEOUT_TRDY)
222
223#define S_PCI_TIMEOUT_RETRY		8
224#define M_PCI_TIMEOUT_RETRY		_SB_MAKEMASK_32(8,S_PCI_TIMEOUT_RETRY)
225#define V_PCI_TIMEOUT_RETRY(x)		_SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_RETRY)
226#define G_PCI_TIMEOUT_RETRY(x)		_SB_GETVALUE_32(x,S_PCI_TIMEOUT_RETRY,M_PCI_TIMEOUT_RETRY)
227
228#define M_PCI_FCONTROL_BAR4_EN		_SB_MAKEMASK1_32(16)
229#define M_PCI_FCONTROL_BAR5_EN		_SB_MAKEMASK1_32(17)
230#define M_PCI_FCONTROL_PTP_EN		_SB_MAKEMASK1_32(18)
231#define M_PCI_FCONTROL_ADAPT_RETRY_EN	_SB_MAKEMASK1_32(19)
232
233#define S_PCI_FCONTROL_MIN_TAR_RETRY	20
234#define M_PCI_FCONTROL_MIN_TAR_RETRY	_SB_MAKEMASK_32(3,S_PCI_FCONTROL_MIN_TAR_RETRY)
235#define V_PCI_FCONTROL_MIN_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY)
236#define G_PCI_FCONTROL_MIN_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY,M_PCI_FCONTROL_MIN_TAR_RETRY)
237
238#define S_PCI_FCONTROL_NOM_TAR_RETRY	23
239#define M_PCI_FCONTROL_NOM_TAR_RETRY	_SB_MAKEMASK_32(4,S_PCI_FCONTROL_NOM_TAR_RETRY)
240#define V_PCI_FCONTROL_NOM_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY)
241#define G_PCI_FCONTROL_NOM_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY,M_PCI_FCONTROL_NOM_TAR_RETRY)
242
243#define S_PCI_FCONTROL_MAX_TAR_RETRY	27
244#define M_PCI_FCONTROL_MAX_TAR_RETRY	_SB_MAKEMASK_32(5,S_PCI_FCONTROL_MAX_TAR_RETRY)
245#define V_PCI_FCONTROL_MAX_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY)
246#define G_PCI_FCONTROL_MAX_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY,M_PCI_FCONTROL_MAX_TAR_RETRY)
247
248/*
249 * BAR0 Map Table Entry (Offsets 0x40-0x80) (Table 8-10)
250 */
251
252#define M_PCI_BAR0MAP_ENABLE		_SB_MAKEMASK1_32(0)
253#define M_PCI_BAR0MAP_SENDLDT		_SB_MAKEMASK1_32(1)
254#define S_PCI_BAR0MAP_ADDR		12
255#define M_PCI_BAR0MAP_ADDR		_SB_MAKEMASK_32(20,S_PCI_BAR0MAP_ADDR)
256
257/*
258 * Additional Status Register (Table 8-11)
259 */
260
261#define M_PCI_ASTATUS_HOTPLUG_EN	_SB_MAKEMASK1_32(0)
262#define M_PCI_ASTATUS_SERR_DET		_SB_MAKEMASK1_32(1)
263#define M_PCI_ASTATUS_TRDYERR		_SB_MAKEMASK1_32(2)
264#define M_PCI_ASTATUS_RETRTYERR		_SB_MAKEMASK1_32(3)
265#define M_PCI_ASTATUS_TRDYINTMASK	_SB_MAKEMASK1_32(4)
266#define M_PCI_ASTATUS_RETRYINTMASK	_SB_MAKEMASK1_32(5)
267#define M_PCI_ASTATUS_SIGNALINTA	_SB_MAKEMASK1_32(6)
268
269#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
270/*
271 * Read Host Register
272 */
273
274#define M_PCI_READHOST_RDHOST	_SB_MAKEMASK1_32(0)
275
276/*
277 * Adaptive Extend Register
278 */
279
280#define S_PCI_ADXTEND_NOM_TAR_RETRY	1
281#define M_PCI_ADXTEND_NOM_TAR_RETRY	_SB_MAKEMASK_32(3,S_PCI_ADXTEND_NOM_TAR_RETRY)
282#define V_PCI_ADXTEND_NOM_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY)
283#define G_PCI_ADXTEND_NOM_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY,M_PCI_ADXTEND_NOM_TAR_RETRY)
284
285#define S_PCI_ADXTEND_MAX_TAR_RETRY	4
286#define M_PCI_ADXTEND_MAX_TAR_RETRY	_SB_MAKEMASK_32(2,S_PCI_ADXTEND_MAX_TAR_RETRY)
287#define V_PCI_ADXTEND_MAX_TAR_RETRY(x)	_SB_MAKEVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY)
288#define G_PCI_ADXTEND_MAX_TAR_RETRY(x)	_SB_GETVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY,M_PCI_ADXTEND_MAX_TAR_RETRY)
289
290#define M_PCI_ADXTEND_DIS_DMAR_IOW_DEP  _SB_MAKEMASK1_32(6)
291#define M_PCI_ADXTEND_DIS_MEMRD_BE      _SB_MAKEMASK1_32(6)
292#endif /* 1250 PASS2 || 112x PASS1 */
293
294
295#endif
296
297
298