cpu.h revision 1.1
11.1Sws/* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 21.1Sws 31.1Sws/* 41.1Sws * Copyright (C) 1995, 1996 Wolfgang Solfrank. 51.1Sws * Copyright (C) 1995, 1996 TooLs GmbH. 61.1Sws * All rights reserved. 71.1Sws * 81.1Sws * Redistribution and use in source and binary forms, with or without 91.1Sws * modification, are permitted provided that the following conditions 101.1Sws * are met: 111.1Sws * 1. Redistributions of source code must retain the above copyright 121.1Sws * notice, this list of conditions and the following disclaimer. 131.1Sws * 2. Redistributions in binary form must reproduce the above copyright 141.1Sws * notice, this list of conditions and the following disclaimer in the 151.1Sws * documentation and/or other materials provided with the distribution. 161.1Sws * 3. All advertising materials mentioning features or use of this software 171.1Sws * must display the following acknowledgement: 181.1Sws * This product includes software developed by TooLs GmbH. 191.1Sws * 4. The name of TooLs GmbH may not be used to endorse or promote products 201.1Sws * derived from this software without specific prior written permission. 211.1Sws * 221.1Sws * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 231.1Sws * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 241.1Sws * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 251.1Sws * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 261.1Sws * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 271.1Sws * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 281.1Sws * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 291.1Sws * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 301.1Sws * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 311.1Sws * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 321.1Sws */ 331.1Sws#ifndef _MACHINE_CPU_H_ 341.1Sws#define _MACHINE_CPU_H_ 351.1Sws 361.1Sws#include <machine/frame.h> 371.1Sws 381.1Swsstruct machvec { 391.1Sws void (*splx) __P((int)); 401.1Sws void (*irq_establish) __P((int, int, void (*)(void *), void *)); 411.1Sws}; 421.1Swsextern struct machvec machine_interface; 431.1Sws 441.1Sws#include <machine/psl.h> 451.1Sws 461.1Sws#define irq_establish(irq, level, handler, arg) \ 471.1Sws ((*machine_interface.irq_establish)((irq), (level), (handler), (arg))) 481.1Sws 491.1Sws#define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 501.1Sws#define CLKF_BASEPRI(frame) ((frame)->pri == 0) 511.1Sws#define CLKF_PC(frame) ((frame)->srr0) 521.1Sws#define CLKF_INTR(frame) ((frame)->depth != 0) 531.1Sws 541.1Sws#define cpu_swapout(p) 551.1Sws#define cpu_wait(p) 561.1Sws 571.1Swsextern void delay __P((unsigned)); 581.1Sws#define DELAY(n) delay(n) 591.1Sws 601.1Swsextern volatile int want_resched; 611.1Swsextern volatile int astpending; 621.1Sws 631.1Sws#define need_resched() (want_resched = 1, astpending = 1) 641.1Sws#define need_proftick(p) ((p)->p_flag |= P_OWEUPC, astpending = 1) 651.1Sws#define signotify(p) (astpending = 1) 661.1Sws 671.1Sws#define CACHELINESIZE 32 /* For now XXX */ 681.1Sws 691.1Swsextern __inline void 701.1Swssyncicache(from, len) 711.1Sws void *from; 721.1Sws int len; 731.1Sws{ 741.1Sws int l = len; 751.1Sws void *p = from; 761.1Sws 771.1Sws do { 781.1Sws asm volatile ("dcbst 0,%0" :: "r"(p)); 791.1Sws p += CACHELINESIZE; 801.1Sws } while ((l -= CACHELINESIZE) > 0); 811.1Sws asm volatile ("sync"); 821.1Sws do { 831.1Sws asm volatile ("icbi 0,%0" :: "r"(from)); 841.1Sws from += CACHELINESIZE; 851.1Sws } while ((len -= CACHELINESIZE) > 0); 861.1Sws asm volatile ("isync"); 871.1Sws} 881.1Sws 891.1Swsextern char *bootpath; 901.1Sws 911.1Sws#endif /* _MACHINE_CPU_H_ */ 92