dec_3min.c revision 1.24
1/* $NetBSD: dec_3min.c,v 1.24 1999/11/15 09:50:24 nisimura Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.24 1999/11/15 09:50:24 nisimura Exp $"); 77 78 79#include <sys/types.h> 80#include <sys/systm.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/reg.h> 85#include <machine/psl.h> 86#include <machine/sysconf.h> 87 88#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 89 90/* all these to get ioasic_base */ 91#include <sys/device.h> /* struct cfdata for.. */ 92#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 93#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 94#include <dev/tc/ioasicvar.h> /* ioasic_base */ 95 96#include <pmax/pmax/turbochannel.h> 97#include <pmax/pmax/machdep.h> 98 99#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 100#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 101 102 103/* 104 * forward declarations 105 */ 106void dec_3min_init __P((void)); 107void dec_3min_bus_reset __P((void)); 108 109void dec_3min_enable_intr 110 __P ((unsigned slotno, int (*handler)(void *), 111 void *sc, int onoff)); 112int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 113void dec_3min_device_register __P((struct device *, void *)); 114void dec_3min_cons_init __P((void)); 115 116 117/* 118 * Local declarations. 119 */ 120void dec_3min_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr, 121 int clockmask)); 122void kn02ba_wbflush __P((void)); 123unsigned kn02ba_clkread __P((void)); 124 125static u_int32_t kmin_tc3_imask; 126 127#ifdef MIPS3 128static unsigned latched_cycle_cnt; 129extern u_int32_t mips3_cycle_count __P((void)); 130#endif 131 132 133void 134dec_3min_init() 135{ 136 extern char cpu_model[]; 137 extern int physmem_boardmax; 138 139 platform.iobus = "tcbus"; 140 platform.bus_reset = dec_3min_bus_reset; 141 platform.cons_init = dec_3min_cons_init; 142 platform.device_register = dec_3min_device_register; 143 platform.iointr = dec_3min_intr; 144 platform.clkread = kn02ba_clkread; 145 146 /* clear any memory errors */ 147 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 148 kn02ba_wbflush(); 149 150 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 151 mips_hardware_intr = dec_3min_intr; 152 tc_enable_interrupt = dec_3min_enable_intr; 153 154 /* 155 * Since all the motherboard interrupts come through the 156 * IOASIC, it has to be turned off for all the spls and 157 * since we don't know what kinds of devices are in the 158 * TURBOchannel option slots, just splhigh(). 159 */ 160 splvec.splbio = MIPS_SPL_0_1_2_3; 161 splvec.splnet = MIPS_SPL_0_1_2_3; 162 splvec.spltty = MIPS_SPL_0_1_2_3; 163 splvec.splimp = MIPS_SPL_0_1_2_3; 164 splvec.splclock = MIPS_SPL_0_1_2_3; 165 splvec.splstatclock = MIPS_SPL_0_1_2_3; 166 167 /* calibrate cpu_mhz value */ 168 dec_3min_mcclock_cpuspeed( 169 (void *)(ioasic_base + IOASIC_SLOT_8_START), MIPS_INT_MASK_3); 170 171 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 172 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 173#if 0 174 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 175 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 176 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 177#endif 178 179 /* sanitize interrupt mask */ 180 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 181 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 182 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 183 184 /* 185 * The kmin memory hardware seems to wrap memory addresses 186 * with 4Mbyte SIMMs, which causes the physmem computation 187 * to lose. Find out how big the SIMMS are and set 188 * max_ physmem accordingly. 189 * XXX Do MAXINEs lose the same way? 190 */ 191 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 192 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 193 == 0) 194 physmem_boardmax = physmem_boardmax >> 2; 195 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 196 197 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 198} 199 200/* 201 * Initalize the memory system and I/O buses. 202 */ 203void 204dec_3min_bus_reset() 205{ 206 207 /* 208 * Reset interrupts, clear any errors from newconf probes 209 */ 210 211 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 212 kn02ba_wbflush(); 213 214 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 215 kn02ba_wbflush(); 216} 217 218void 219dec_3min_cons_init() 220{ 221 /* notyet */ 222} 223 224 225void 226dec_3min_device_register(dev, aux) 227 struct device *dev; 228 void *aux; 229{ 230 panic("dec_3min_device_register unimplemented"); 231} 232 233 234void 235dec_3min_enable_intr(slotno, handler, sc, on) 236 unsigned int slotno; 237 int (*handler) __P((void *)); 238 void *sc; 239 int on; 240{ 241 unsigned mask; 242 243 switch (slotno) { 244 /* slots 0-2 don't interrupt through the IOASIC. */ 245 case 0: 246 mask = MIPS_INT_MASK_0; break; 247 case 1: 248 mask = MIPS_INT_MASK_1; break; 249 case 2: 250 mask = MIPS_INT_MASK_2; break; 251 252 case KMIN_SCSI_SLOT: 253 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 254 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 255 break; 256 257 case KMIN_LANCE_SLOT: 258 mask = KMIN_INTR_LANCE; 259 break; 260 case KMIN_SCC0_SLOT: 261 mask = KMIN_INTR_SCC_0; 262 break; 263 case KMIN_SCC1_SLOT: 264 mask = KMIN_INTR_SCC_1; 265 break; 266 case KMIN_ASIC_SLOT: 267 mask = KMIN_INTR_ASIC; 268 break; 269 default: 270 return; 271 } 272 273#if defined(DEBUG) || defined(DIAGNOSTIC) 274 printf("3MIN: imask %lx, %sabling slot %d, sc %p handler %p\n", 275 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 276#endif 277 278 /* 279 * Enable the interrupt handler, and if it's an IOASIC 280 * slot, set the IOASIC interrupt mask. 281 * Otherwise, set the appropriate spl level in the R3000 282 * register. 283 * Be careful to set handlers before enabling, and disable 284 * interrupts before clearing handlers. 285 */ 286 287 if (on) { 288 /* Set the interrupt handler and argument ... */ 289 tc_slot_info[slotno].intr = handler; 290 tc_slot_info[slotno].sc = sc; 291 292 /* ... and set the relevant mask */ 293 if (slotno <= 2) { 294 /* it's an option slot */ 295 int s = splhigh(); 296 s |= mask; 297 splx(s); 298 } else { 299 /* it's a baseboard device going via the ASIC */ 300 kmin_tc3_imask |= mask; 301 } 302 } else { 303 /* Clear the relevant mask... */ 304 if (slotno <= 2) { 305 /* it's an option slot */ 306 int s = splhigh(); 307 printf("kmin_intr: cannot disable option slot %d\n", 308 slotno); 309 s &= ~mask; 310 splx(s); 311 } else { 312 /* it's a baseboard device going via the ASIC */ 313 kmin_tc3_imask &= ~mask; 314 } 315 /* ... and clear the handler */ 316 tc_slot_info[slotno].intr = 0; 317 tc_slot_info[slotno].sc = 0; 318 } 319} 320 321 322 323/* 324 * 3min hardware interrupts. (DECstation 5000/1xx) 325 */ 326int 327dec_3min_intr(cpumask, pc, status, cause) 328 unsigned cpumask; 329 unsigned pc; 330 unsigned status; 331 unsigned cause; 332{ 333 static int user_warned = 0; 334 static int intr_depth = 0; 335 u_int32_t old_mask; 336 337 intr_depth++; 338 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 339 340 if (cpumask & MIPS_INT_MASK_4) 341 prom_haltbutton(); 342 343 if (cpumask & MIPS_INT_MASK_3) { 344 /* NB: status & MIPS_INT_MASK3 must also be set */ 345 /* masked interrupts are still observable */ 346 u_int32_t intr, imsk, turnoff; 347 348 turnoff = 0; 349 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 350 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 351 intr &= imsk; 352 353 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 354 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 355#ifdef notdef 356 asc_dma_intr(); 357#endif 358 } 359 360 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 361 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 362 363 if (intr & IOASIC_INTR_LANCE_READ_E) 364 turnoff |= IOASIC_INTR_LANCE_READ_E; 365 366 if (turnoff) 367 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 368 369 if (intr & KMIN_INTR_TIMEOUT) 370 kn02ba_errintr(); 371 372 if (intr & KMIN_INTR_CLOCK) { 373 struct clockframe cf; 374 375 __asm __volatile("lbu $0,48(%0)" :: 376 "r"(ioasic_base + IOASIC_SLOT_8_START)); 377#ifdef MIPS3 378 if (CPUISMIPS3) { 379 latched_cycle_cnt = mips3_cycle_count(); 380 } 381#endif 382 cf.pc = pc; 383 cf.sr = status; 384 hardclock(&cf); 385 intrcnt[HARDCLOCK]++; 386 } 387 388 /* If clock interrups were enabled, re-enable them ASAP. */ 389 if (old_mask & KMIN_INTR_CLOCK) { 390 /* ioctl interrupt mask to splclock and higher */ 391 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 392 = old_mask & 393 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 394 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 395 kn02ba_wbflush(); 396 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 397 } 398 399 if (intr_depth > 1) 400 goto done; 401 402 if ((intr & KMIN_INTR_SCC_0) && 403 tc_slot_info[KMIN_SCC0_SLOT].intr) { 404 (*(tc_slot_info[KMIN_SCC0_SLOT].intr)) 405 (tc_slot_info[KMIN_SCC0_SLOT].sc); 406 intrcnt[SERIAL0_INTR]++; 407 } 408 409 if ((intr & KMIN_INTR_SCC_1) && 410 tc_slot_info[KMIN_SCC1_SLOT].intr) { 411 (*(tc_slot_info[KMIN_SCC1_SLOT].intr)) 412 (tc_slot_info[KMIN_SCC1_SLOT].sc); 413 intrcnt[SERIAL1_INTR]++; 414 } 415 416#ifdef notyet /* untested */ 417 /* If tty interrupts were enabled, re-enable them ASAP. */ 418 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 419 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 420 *imaskp = old_mask & 421 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 422 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 423 kn02ba_wbflush(); 424 } 425 426 /* XXX until we know about SPLs of TC options. */ 427 if (intr_depth > 1) 428 goto done; 429#endif 430 if ((intr & IOASIC_INTR_LANCE) && 431 tc_slot_info[KMIN_LANCE_SLOT].intr) { 432 (*(tc_slot_info[KMIN_LANCE_SLOT].intr)) 433 (tc_slot_info[KMIN_LANCE_SLOT].sc); 434 intrcnt[LANCE_INTR]++; 435 } 436 437 if ((intr & IOASIC_INTR_SCSI) && 438 tc_slot_info[KMIN_SCSI_SLOT].intr) { 439 (*(tc_slot_info[KMIN_SCSI_SLOT].intr)) 440 (tc_slot_info[KMIN_SCSI_SLOT].sc); 441 intrcnt[SCSI_INTR]++; 442 } 443 444 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 445 printf("%s\n", "Power supply ok now."); 446 user_warned = 0; 447 } 448 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 449 user_warned++; 450 printf("%s\n", "Power supply overheating"); 451 } 452 } 453 if ((cpumask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) { 454 (*tc_slot_info[0].intr)(tc_slot_info[0].sc); 455 intrcnt[SLOT0_INTR]++; 456 } 457 458 if ((cpumask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) { 459 (*tc_slot_info[1].intr)(tc_slot_info[1].sc); 460 intrcnt[SLOT1_INTR]++; 461 } 462 if ((cpumask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) { 463 (*tc_slot_info[2].intr)(tc_slot_info[2].sc); 464 intrcnt[SLOT2_INTR]++; 465 } 466 467done: 468 /* restore entry state */ 469 splhigh(); 470 intr_depth--; 471 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 472 473 474 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 475} 476 477 478 479/* 480 ************************************************************************ 481 * Extra functions 482 ************************************************************************ 483 */ 484 485 486 487 488/* 489 * Count instructions between 4ms mcclock interrupt requests, 490 * using the ioasic clock-interrupt-pending bit to determine 491 * when clock ticks occur. 492 * Set up iosiac to allow only clock interrupts, then 493 * call 494 */ 495void 496dec_3min_mcclock_cpuspeed(mcclock_addr, clockmask) 497 volatile struct chiptime *mcclock_addr; 498 int clockmask; 499{ 500 u_int32_t saved_imask; 501 502 saved_imask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 503 504 /* Allow only clock interrupts through ioasic. */ 505 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 506 kn02ba_wbflush(); 507 508 mc_cpuspeed(mcclock_addr, clockmask); 509 510 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = saved_imask; 511 kn02ba_wbflush(); 512} 513 514void 515kn02ba_wbflush() 516{ 517 /* read twice IOASIC_IMSK */ 518 __asm __volatile("lw $0,%0; lw $0,%0" :: "i"(0xbc040120)); 519} 520 521unsigned 522kn02ba_clkread() 523{ 524#ifdef MIPS3 525 if (CPUISMIPS3) { 526 u_int32_t mips3_cycles; 527 528 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 529 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 530 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 531 (mips3_cycles >> 11)); 532 } 533#endif 534 return 0; 535} 536