dec_3min.c revision 1.31
1/* $NetBSD: dec_3min.c,v 1.31 2000/01/09 03:55:58 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.31 2000/01/09 03:55:58 simonb Exp $"); 77 78 79#include <sys/types.h> 80#include <sys/systm.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/locore.h> 85#include <machine/reg.h> 86#include <machine/psl.h> 87#include <machine/sysconf.h> 88 89#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 90 91/* all these to get ioasic_base */ 92#include <sys/device.h> /* struct cfdata for.. */ 93#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 94#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 95#include <dev/tc/ioasicvar.h> /* ioasic_base */ 96 97#include <pmax/pmax/turbochannel.h> 98#include <pmax/pmax/machdep.h> 99 100#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 101#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 102 103 104/* 105 * forward declarations 106 */ 107void dec_3min_init __P((void)); /* XXX */ 108static void dec_3min_bus_reset __P((void)); 109static void dec_3min_enable_intr __P((unsigned slotno, 110 int (*handler)(void *), void *sc, int onoff)); 111static int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 112static void dec_3min_device_register __P((struct device *, void *)); 113static void dec_3min_cons_init __P((void)); 114 115static void kn02ba_wbflush __P((void)); 116static unsigned kn02ba_clkread __P((void)); 117 118 119/* 120 * Local declarations. 121 */ 122static u_int32_t kmin_tc3_imask; 123 124#ifdef MIPS3 125static unsigned latched_cycle_cnt; 126#endif 127 128 129void 130dec_3min_init() 131{ 132 int physmem_boardmax; 133 134 platform.iobus = "tcbus"; 135 platform.bus_reset = dec_3min_bus_reset; 136 platform.cons_init = dec_3min_cons_init; 137 platform.device_register = dec_3min_device_register; 138 platform.iointr = dec_3min_intr; 139 platform.memsize = memsize_scan; 140 platform.clkread = kn02ba_clkread; 141 142 /* clear any memory errors */ 143 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 144 kn02ba_wbflush(); 145 146 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 147 mips_hardware_intr = dec_3min_intr; 148 tc_enable_interrupt = dec_3min_enable_intr; 149 150 /* 151 * Since all the motherboard interrupts come through the 152 * IOASIC, it has to be turned off for all the spls and 153 * since we don't know what kinds of devices are in the 154 * TURBOchannel option slots, just splhigh(). 155 */ 156 splvec.splbio = MIPS_SPL_0_1_2_3; 157 splvec.splnet = MIPS_SPL_0_1_2_3; 158 splvec.spltty = MIPS_SPL_0_1_2_3; 159 splvec.splimp = MIPS_SPL_0_1_2_3; 160 splvec.splclock = MIPS_SPL_0_1_2_3; 161 splvec.splstatclock = MIPS_SPL_0_1_2_3; 162 163 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 164 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 165 /* calibrate cpu_mhz value */ 166 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 167 168 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 169 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 170#if 0 171 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 172 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 173 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 174#endif 175 176 /* sanitize interrupt mask */ 177 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 178 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 179 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 180 181 /* 182 * The kmin memory hardware seems to wrap memory addresses 183 * with 4Mbyte SIMMs, which causes the physmem computation 184 * to lose. Find out how big the SIMMS are and set 185 * max_ physmem accordingly. 186 * XXX Do MAXINEs lose the same way? 187 */ 188 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 189 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 190 == 0) 191 physmem_boardmax = physmem_boardmax >> 2; 192 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 193 194 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 195} 196 197/* 198 * Initalize the memory system and I/O buses. 199 */ 200static void 201dec_3min_bus_reset() 202{ 203 204 /* 205 * Reset interrupts, clear any errors from newconf probes 206 */ 207 208 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 209 kn02ba_wbflush(); 210 211 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 212 kn02ba_wbflush(); 213} 214 215static void 216dec_3min_cons_init() 217{ 218 /* notyet */ 219} 220 221 222static void 223dec_3min_device_register(dev, aux) 224 struct device *dev; 225 void *aux; 226{ 227 panic("dec_3min_device_register unimplemented"); 228} 229 230 231static void 232dec_3min_enable_intr(slotno, handler, sc, on) 233 unsigned int slotno; 234 int (*handler) __P((void *)); 235 void *sc; 236 int on; 237{ 238 unsigned mask; 239 240 switch (slotno) { 241 /* slots 0-2 don't interrupt through the IOASIC. */ 242 case 0: 243 mask = MIPS_INT_MASK_0; break; 244 case 1: 245 mask = MIPS_INT_MASK_1; break; 246 case 2: 247 mask = MIPS_INT_MASK_2; break; 248 249 case KMIN_SCSI_SLOT: 250 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 251 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 252 break; 253 254 case KMIN_LANCE_SLOT: 255 mask = KMIN_INTR_LANCE; 256 break; 257 case KMIN_SCC0_SLOT: 258 mask = KMIN_INTR_SCC_0; 259 break; 260 case KMIN_SCC1_SLOT: 261 mask = KMIN_INTR_SCC_1; 262 break; 263 case KMIN_ASIC_SLOT: 264 mask = KMIN_INTR_ASIC; 265 break; 266 default: 267 return; 268 } 269 270#if defined(DEBUG) || defined(DIAGNOSTIC) 271 printf("3MIN: imask %x, %sabling slot %d, sc %p handler %p\n", 272 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 273#endif 274 275 /* 276 * Enable the interrupt handler, and if it's an IOASIC 277 * slot, set the IOASIC interrupt mask. 278 * Otherwise, set the appropriate spl level in the R3000 279 * register. 280 * Be careful to set handlers before enabling, and disable 281 * interrupts before clearing handlers. 282 */ 283 284 if (on) { 285 /* Set the interrupt handler and argument ... */ 286 tc_slot_info[slotno].intr = handler; 287 tc_slot_info[slotno].sc = sc; 288 289 /* ... and set the relevant mask */ 290 if (slotno <= 2) { 291 /* it's an option slot */ 292 int s = splhigh(); 293 s |= mask; 294 splx(s); 295 } else { 296 /* it's a baseboard device going via the ASIC */ 297 kmin_tc3_imask |= mask; 298 } 299 } else { 300 /* Clear the relevant mask... */ 301 if (slotno <= 2) { 302 /* it's an option slot */ 303 int s = splhigh(); 304 printf("kmin_intr: cannot disable option slot %d\n", 305 slotno); 306 s &= ~mask; 307 splx(s); 308 } else { 309 /* it's a baseboard device going via the ASIC */ 310 kmin_tc3_imask &= ~mask; 311 } 312 /* ... and clear the handler */ 313 tc_slot_info[slotno].intr = 0; 314 tc_slot_info[slotno].sc = 0; 315 } 316 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 317 kn02ba_wbflush(); 318} 319 320 321 322/* 323 * 3min hardware interrupts. (DECstation 5000/1xx) 324 */ 325static int 326dec_3min_intr(cpumask, pc, status, cause) 327 unsigned cpumask; 328 unsigned pc; 329 unsigned status; 330 unsigned cause; 331{ 332 static int user_warned = 0; 333 static int intr_depth = 0; 334 u_int32_t old_mask; 335 336 intr_depth++; 337 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 338 339 if (cpumask & MIPS_INT_MASK_4) 340 prom_haltbutton(); 341 342 if (cpumask & MIPS_INT_MASK_3) { 343 /* NB: status & MIPS_INT_MASK3 must also be set */ 344 /* masked interrupts are still observable */ 345 u_int32_t intr, imsk, turnoff; 346 347 turnoff = 0; 348 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 349 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 350 intr &= imsk; 351 352 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 353 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 354#ifdef notdef 355 asc_dma_intr(); 356#endif 357 } 358 359 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 360 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 361 362 if (intr & IOASIC_INTR_LANCE_READ_E) 363 turnoff |= IOASIC_INTR_LANCE_READ_E; 364 365 if (turnoff) 366 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 367 368 if (intr & KMIN_INTR_TIMEOUT) 369 kn02ba_errintr(); 370 371 if (intr & KMIN_INTR_CLOCK) { 372 struct clockframe cf; 373 374 __asm __volatile("lbu $0,48(%0)" :: 375 "r"(ioasic_base + IOASIC_SLOT_8_START)); 376#ifdef MIPS3 377 if (CPUISMIPS3) { 378 latched_cycle_cnt = mips3_cycle_count(); 379 } 380#endif 381 cf.pc = pc; 382 cf.sr = status; 383 hardclock(&cf); 384 intrcnt[HARDCLOCK]++; 385 } 386 387 /* If clock interrups were enabled, re-enable them ASAP. */ 388 if (old_mask & KMIN_INTR_CLOCK) { 389 /* ioctl interrupt mask to splclock and higher */ 390 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 391 = old_mask & 392 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 393 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 394 kn02ba_wbflush(); 395 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 396 } 397 398 if (intr_depth > 1) 399 goto done; 400 401 if ((intr & KMIN_INTR_SCC_0) && 402 tc_slot_info[KMIN_SCC0_SLOT].intr) { 403 (*(tc_slot_info[KMIN_SCC0_SLOT].intr)) 404 (tc_slot_info[KMIN_SCC0_SLOT].sc); 405 intrcnt[SERIAL0_INTR]++; 406 } 407 408 if ((intr & KMIN_INTR_SCC_1) && 409 tc_slot_info[KMIN_SCC1_SLOT].intr) { 410 (*(tc_slot_info[KMIN_SCC1_SLOT].intr)) 411 (tc_slot_info[KMIN_SCC1_SLOT].sc); 412 intrcnt[SERIAL1_INTR]++; 413 } 414 415#ifdef notyet /* untested */ 416 /* If tty interrupts were enabled, re-enable them ASAP. */ 417 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 418 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 419 *imaskp = old_mask & 420 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 421 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 422 kn02ba_wbflush(); 423 } 424 425 /* XXX until we know about SPLs of TC options. */ 426 if (intr_depth > 1) 427 goto done; 428#endif 429 if ((intr & IOASIC_INTR_LANCE) && 430 tc_slot_info[KMIN_LANCE_SLOT].intr) { 431 (*(tc_slot_info[KMIN_LANCE_SLOT].intr)) 432 (tc_slot_info[KMIN_LANCE_SLOT].sc); 433 intrcnt[LANCE_INTR]++; 434 } 435 436 if ((intr & IOASIC_INTR_SCSI) && 437 tc_slot_info[KMIN_SCSI_SLOT].intr) { 438 (*(tc_slot_info[KMIN_SCSI_SLOT].intr)) 439 (tc_slot_info[KMIN_SCSI_SLOT].sc); 440 intrcnt[SCSI_INTR]++; 441 } 442 443 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 444 printf("%s\n", "Power supply ok now."); 445 user_warned = 0; 446 } 447 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 448 user_warned++; 449 printf("%s\n", "Power supply overheating"); 450 } 451 } 452 if ((cpumask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) { 453 (*tc_slot_info[0].intr)(tc_slot_info[0].sc); 454 intrcnt[SLOT0_INTR]++; 455 } 456 457 if ((cpumask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) { 458 (*tc_slot_info[1].intr)(tc_slot_info[1].sc); 459 intrcnt[SLOT1_INTR]++; 460 } 461 if ((cpumask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) { 462 (*tc_slot_info[2].intr)(tc_slot_info[2].sc); 463 intrcnt[SLOT2_INTR]++; 464 } 465 466done: 467 /* restore entry state */ 468 splhigh(); 469 intr_depth--; 470 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 471 472 473 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 474} 475 476 477 478/* 479 ************************************************************************ 480 * Extra functions 481 ************************************************************************ 482 */ 483 484static void 485kn02ba_wbflush() 486{ 487 /* read twice IOASIC_IMSK */ 488 __asm __volatile("lw $0,%0; lw $0,%0" :: 489 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 490} 491 492static unsigned 493kn02ba_clkread() 494{ 495#ifdef MIPS3 496 if (CPUISMIPS3) { 497 u_int32_t mips3_cycles; 498 499 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 500 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 501 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 502 (mips3_cycles >> 11)); 503 } 504#endif 505 return 0; 506} 507