dec_3min.c revision 1.35
1/* $NetBSD: dec_3min.c,v 1.35 2000/02/29 04:41:52 nisimura Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.35 2000/02/29 04:41:52 nisimura Exp $"); 77 78#include <sys/param.h> 79#include <sys/systm.h> 80#include <sys/device.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/sysconf.h> 85 86#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 87 88/* all these to get ioasic_base */ 89#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 90#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 91#include <dev/tc/ioasicvar.h> /* ioasic_base */ 92 93#include <pmax/pmax/machdep.h> 94#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 95#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 96#include <pmax/tc/sccvar.h> 97 98#include "rasterconsole.h" 99 100void dec_3min_init __P((void)); /* XXX */ 101static void dec_3min_bus_reset __P((void)); 102static void dec_3min_cons_init __P((void)); 103static void dec_3min_device_register __P((struct device *, void *)); 104static int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 105static void dec_3min_intr_establish __P((struct device *, void *, 106 int, int (*)(void *), void *)); 107 108static void kn02ba_wbflush __P((void)); 109static unsigned kn02ba_clkread __P((void)); 110 111 112/* 113 * Local declarations. 114 */ 115static u_int32_t kmin_tc3_imask; 116 117#ifdef MIPS3 118static unsigned latched_cycle_cnt; 119#endif 120 121 122void 123dec_3min_init() 124{ 125 int physmem_boardmax; 126 127 platform.iobus = "tcbus"; 128 platform.bus_reset = dec_3min_bus_reset; 129 platform.cons_init = dec_3min_cons_init; 130 platform.device_register = dec_3min_device_register; 131 platform.iointr = dec_3min_intr; 132 platform.intr_establish = dec_3min_intr_establish; 133 platform.memsize = memsize_scan; 134 platform.clkread = kn02ba_clkread; 135 136 /* clear any memory errors */ 137 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 138 kn02ba_wbflush(); 139 140 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 141 mips_hardware_intr = dec_3min_intr; 142 143 /* 144 * Since all the motherboard interrupts come through the 145 * IOASIC, it has to be turned off for all the spls and 146 * since we don't know what kinds of devices are in the 147 * TURBOchannel option slots, just splhigh(). 148 */ 149 splvec.splbio = MIPS_SPL_0_1_2_3; 150 splvec.splnet = MIPS_SPL_0_1_2_3; 151 splvec.spltty = MIPS_SPL_0_1_2_3; 152 splvec.splimp = MIPS_SPL_0_1_2_3; 153 splvec.splclock = MIPS_SPL_0_1_2_3; 154 splvec.splstatclock = MIPS_SPL_0_1_2_3; 155 156 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 157 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 158 /* calibrate cpu_mhz value */ 159 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 160 161 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 162 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 163#if 0 164 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 165 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 166 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 167#endif 168 169 /* sanitize interrupt mask */ 170 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 171 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 172 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 173 174 /* 175 * The kmin memory hardware seems to wrap memory addresses 176 * with 4Mbyte SIMMs, which causes the physmem computation 177 * to lose. Find out how big the SIMMS are and set 178 * max_ physmem accordingly. 179 * XXX Do MAXINEs lose the same way? 180 */ 181 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 182 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 183 == 0) 184 physmem_boardmax = physmem_boardmax >> 2; 185 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 186 187 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 188} 189 190/* 191 * Initalize the memory system and I/O buses. 192 */ 193static void 194dec_3min_bus_reset() 195{ 196 197 /* 198 * Reset interrupts, clear any errors from newconf probes 199 */ 200 201 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 202 kn02ba_wbflush(); 203 204 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 205 kn02ba_wbflush(); 206} 207 208static void 209dec_3min_cons_init() 210{ 211 int kbd, crt, screen; 212 extern int tcfb_cnattach __P((int)); /* XXX */ 213 214 kbd = crt = screen = 0; 215 prom_findcons(&kbd, &crt, &screen); 216 217 if (screen > 0) { 218#if NRASTERCONSOLE > 0 219 if (tcfb_cnattach(crt) > 0) { 220 scc_lk201_cnattach(ioasic_base, 0x180000); 221 return; 222 } 223#endif 224 printf("No framebuffer device configured for slot %d: ", crt); 225 printf("using serial console\n"); 226 } 227 /* 228 * Delay to allow PROM putchars to complete. 229 * FIFO depth * character time, 230 * character time = (1000000 / (defaultrate / 10)) 231 */ 232 DELAY(160000000 / 9600); /* XXX */ 233 234 scc_cnattach(ioasic_base, 0x180000); 235} 236 237 238static void 239dec_3min_device_register(dev, aux) 240 struct device *dev; 241 void *aux; 242{ 243 panic("dec_3min_device_register unimplemented"); 244} 245 246 247static void 248dec_3min_intr_establish(dev, cookie, level, handler, arg) 249 struct device *dev; 250 void *cookie; 251 int level; 252 int (*handler) __P((void *)); 253 void *arg; 254{ 255 unsigned mask; 256 257 switch ((int)cookie) { 258 /* slots 0-2 don't interrupt through the IOASIC. */ 259 case SYS_DEV_OPT0: 260 mask = MIPS_INT_MASK_0; 261 break; 262 case SYS_DEV_OPT1: 263 mask = MIPS_INT_MASK_1; 264 break; 265 case SYS_DEV_OPT2: 266 mask = MIPS_INT_MASK_2; 267 break; 268 269 case SYS_DEV_SCSI: 270 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 271 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 272 break; 273 case SYS_DEV_LANCE: 274 mask = KMIN_INTR_LANCE; 275 break; 276 case SYS_DEV_SCC0: 277 mask = KMIN_INTR_SCC_0; 278 break; 279 case SYS_DEV_SCC1: 280 mask = KMIN_INTR_SCC_1; 281 break; 282 default: 283#ifdef DIAGNOSTIC 284 printf("warning: enabling unknown intr %x\n", (int)cookie); 285#endif 286 return; 287 } 288 289#if defined(DEBUG) || defined(DIAGNOSTIC) 290 printf("3MIN: imask %x, %sabling slot %d, sc %p handler %p\n", 291 kmin_tc3_imask, (on? "en" : "dis"), (int)cookie, sc, handler); 292#endif 293 294 /* 295 * Enable the interrupt handler, and if it's an IOASIC 296 * slot, set the IOASIC interrupt mask. 297 * Otherwise, set the appropriate spl level in the R3000 298 * register. 299 * Be careful to set handlers before enabling, and disable 300 * interrupts before clearing handlers. 301 */ 302 303 /* Set the interrupt handler and argument ... */ 304 intrtab[(int)cookie].ih_func = handler; 305 intrtab[(int)cookie].ih_arg = arg; 306 /* ... and set the relevant mask */ 307 switch ((int)cookie) { 308 case SYS_DEV_OPT0: 309 case SYS_DEV_OPT1: 310 case SYS_DEV_OPT2: 311 /* it's an option slot */ 312 { 313 int s = splhigh(); 314 s |= mask; 315 splx(s); 316 } 317 break; 318 default: 319 /* it's a baseboard device going via the IOASIC */ 320 kmin_tc3_imask |= mask; 321 break; 322 } 323 324 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 325 kn02ba_wbflush(); 326} 327 328 329#define CHECKINTR(slot, bits) \ 330 do { \ 331 if (can_serve & (bits)) { \ 332 intrcnt[slot] += 1; \ 333 (*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \ 334 } \ 335 } while (0) 336 337static int 338dec_3min_intr(cpumask, pc, status, cause) 339 unsigned cpumask; 340 unsigned pc; 341 unsigned status; 342 unsigned cause; 343{ 344 static int user_warned = 0; 345 static int intr_depth = 0; 346 u_int32_t old_mask; 347 348 intr_depth++; 349 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 350 351 if (cpumask & MIPS_INT_MASK_4) 352 prom_haltbutton(); 353 354 if (cpumask & MIPS_INT_MASK_3) { 355 /* NB: status & MIPS_INT_MASK3 must also be set */ 356 /* masked interrupts are still observable */ 357 u_int32_t intr, imsk, can_serve, turnoff; 358 359 turnoff = 0; 360 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 361 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 362 can_serve = intr & imsk; 363 364 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 365 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 366#ifdef notdef 367 asc_dma_intr(); 368#endif 369 } 370 371 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 372 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 373 374 if (intr & IOASIC_INTR_LANCE_READ_E) 375 turnoff |= IOASIC_INTR_LANCE_READ_E; 376 377 if (turnoff) 378 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 379 380 if (intr & KMIN_INTR_TIMEOUT) 381 kn02ba_errintr(); 382 383 if (intr & KMIN_INTR_CLOCK) { 384 struct clockframe cf; 385 386 __asm __volatile("lbu $0,48(%0)" :: 387 "r"(ioasic_base + IOASIC_SLOT_8_START)); 388#ifdef MIPS3 389 if (CPUISMIPS3) { 390 latched_cycle_cnt = mips3_cycle_count(); 391 } 392#endif 393 cf.pc = pc; 394 cf.sr = status; 395 hardclock(&cf); 396 intrcnt[HARDCLOCK]++; 397 } 398 399 /* If clock interrups were enabled, re-enable them ASAP. */ 400 if (old_mask & KMIN_INTR_CLOCK) { 401 /* ioctl interrupt mask to splclock and higher */ 402 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 403 = old_mask & 404 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 405 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 406 kn02ba_wbflush(); 407 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 408 } 409 410 if (intr_depth > 1) 411 goto done; 412 413 CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); 414 CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1); 415 416#ifdef notyet /* untested */ 417 /* If tty interrupts were enabled, re-enable them ASAP. */ 418 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 419 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 420 *imaskp = old_mask & 421 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 422 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 423 kn02ba_wbflush(); 424 } 425 426 /* XXX until we know about SPLs of TC options. */ 427 if (intr_depth > 1) 428 goto done; 429#endif 430 CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE); 431 CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI); 432 433 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 434 printf("%s\n", "Power supply ok now."); 435 user_warned = 0; 436 } 437 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 438 user_warned++; 439 printf("%s\n", "Power supply overheating"); 440 } 441 } 442 if ((cpumask & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) { 443 (*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg); 444 intrcnt[SYS_DEV_OPT0]++; 445 } 446 447 if ((cpumask & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) { 448 (*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg); 449 intrcnt[SYS_DEV_OPT1]++; 450 } 451 if ((cpumask & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) { 452 (*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg); 453 intrcnt[SYS_DEV_OPT2]++; 454 } 455 456done: 457 /* restore entry state */ 458 splhigh(); 459 intr_depth--; 460 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 461 462 463 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 464} 465 466 467 468/* 469 ************************************************************************ 470 * Extra functions 471 ************************************************************************ 472 */ 473 474static void 475kn02ba_wbflush() 476{ 477 /* read twice IOASIC_IMSK */ 478 __asm __volatile("lw $0,%0; lw $0,%0" :: 479 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 480} 481 482static unsigned 483kn02ba_clkread() 484{ 485#ifdef MIPS3 486 if (CPUISMIPS3) { 487 u_int32_t mips3_cycles; 488 489 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 490 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 491 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 492 (mips3_cycles >> 11)); 493 } 494#endif 495 return 0; 496} 497