dec_3min.c revision 1.58
1/* $NetBSD: dec_3min.c,v 1.58 2007/12/03 15:34:10 ad Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1992, 1993 35 * The Regents of the University of California. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * the Systems Programming Group of the University of Utah Computer 39 * Science Department, The Mach Operating System project at 40 * Carnegie-Mellon University and Ralph Campbell. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. Neither the name of the University nor the names of its contributors 51 * may be used to endorse or promote products derived from this software 52 * without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 67 */ 68/* 69 * Copyright (c) 1988 University of Utah. 70 * 71 * This code is derived from software contributed to Berkeley by 72 * the Systems Programming Group of the University of Utah Computer 73 * Science Department, The Mach Operating System project at 74 * Carnegie-Mellon University and Ralph Campbell. 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions 78 * are met: 79 * 1. Redistributions of source code must retain the above copyright 80 * notice, this list of conditions and the following disclaimer. 81 * 2. Redistributions in binary form must reproduce the above copyright 82 * notice, this list of conditions and the following disclaimer in the 83 * documentation and/or other materials provided with the distribution. 84 * 3. All advertising materials mentioning features or use of this software 85 * must display the following acknowledgement: 86 * This product includes software developed by the University of 87 * California, Berkeley and its contributors. 88 * 4. Neither the name of the University nor the names of its contributors 89 * may be used to endorse or promote products derived from this software 90 * without specific prior written permission. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 105 */ 106 107#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 108 109__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.58 2007/12/03 15:34:10 ad Exp $"); 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/device.h> 114 115#include <machine/cpu.h> 116#include <machine/intr.h> 117#include <machine/sysconf.h> 118 119#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 120 121/* all these to get ioasic_base */ 122#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 123#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 124#include <dev/tc/ioasicvar.h> /* ioasic_base */ 125 126#include <pmax/pmax/machdep.h> 127#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 128#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 129 130#include <pmax/pmax/cons.h> 131#include <dev/ic/z8530sc.h> 132#include <dev/tc/zs_ioasicvar.h> 133#include "wsdisplay.h" 134 135void dec_3min_init __P((void)); /* XXX */ 136static void dec_3min_bus_reset __P((void)); 137static void dec_3min_cons_init __P((void)); 138static void dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 139static void dec_3min_intr_establish __P((struct device *, void *, 140 int, int (*)(void *), void *)); 141 142static void kn02ba_wbflush __P((void)); 143static unsigned kn02ba_clkread __P((void)); 144 145 146/* 147 * Local declarations. 148 */ 149static u_int32_t kmin_tc3_imask; 150 151#ifdef MIPS3 152static unsigned latched_cycle_cnt; 153#endif 154 155static const int dec_3min_ipl2spl_table[] = { 156 [IPL_NONE] = 0, 157 [IPL_SOFTCLOCK] = _SPL_SOFTCLOCK, 158 [IPL_SOFTNET] = _SPL_SOFTNET, 159 /* 160 * Since all the motherboard interrupts come through the 161 * IOASIC, it has to be turned off for all the spls and 162 * since we don't know what kinds of devices are in the 163 * TURBOchannel option slots, just splhigh(). 164 */ 165 [IPL_VM] = MIPS_SPL_0_1_2_3, 166 [IPL_SCHED] = MIPS_SPL_0_1_2_3, 167 [IPL_HIGH] = MIPS_SPL_0_1_2_3, 168}; 169 170void 171dec_3min_init() 172{ 173 platform.iobus = "tcbus"; 174 platform.bus_reset = dec_3min_bus_reset; 175 platform.cons_init = dec_3min_cons_init; 176 platform.iointr = dec_3min_intr; 177 platform.intr_establish = dec_3min_intr_establish; 178 platform.memsize = memsize_bitmap; 179 platform.clkread = kn02ba_clkread; 180 181 /* clear any memory errors */ 182 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 183 kn02ba_wbflush(); 184 185 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 186 187 ipl2spl_table = dec_3min_ipl2spl_table; 188 189 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 190 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 191 /* calibrate cpu_mhz value */ 192 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 193 194 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 195 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 196#if 0 197 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 198 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 199 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 200#endif 201 202 /* sanitize interrupt mask */ 203 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 204 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 205 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 206 207 /* 208 * The kmin memory hardware seems to wrap memory addresses 209 * with 4Mbyte SIMMs, which causes the physmem computation 210 * to lose. Find out how big the SIMMS are and set 211 * max_ physmem accordingly. 212 * XXX Do MAXINEs lose the same way? 213 */ 214 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 215 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 216 == 0) 217 physmem_boardmax = physmem_boardmax >> 2; 218 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 219 220 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 221} 222 223/* 224 * Initialize the memory system and I/O buses. 225 */ 226static void 227dec_3min_bus_reset() 228{ 229 230 /* 231 * Reset interrupts, clear any errors from newconf probes 232 */ 233 234 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 235 kn02ba_wbflush(); 236 237 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 238 kn02ba_wbflush(); 239} 240 241static void 242dec_3min_cons_init() 243{ 244 int kbd, crt, screen; 245 246 kbd = crt = screen = 0; 247 prom_findcons(&kbd, &crt, &screen); 248 249 if (screen > 0) { 250#if NWSDISPLAY > 0 251 if (tcfb_cnattach(crt) > 0) { 252 zs_ioasic_lk201_cnattach(ioasic_base, 0x180000, 0); 253 return; 254 } 255#endif 256 printf("No framebuffer device configured for slot %d: ", crt); 257 printf("using serial console\n"); 258 } 259 /* 260 * Delay to allow PROM putchars to complete. 261 * FIFO depth * character time, 262 * character time = (1000000 / (defaultrate / 10)) 263 */ 264 DELAY(160000000 / 9600); /* XXX */ 265 266 zs_ioasic_cnattach(ioasic_base, 0x180000, 1); 267} 268 269static void 270dec_3min_intr_establish(dev, cookie, level, handler, arg) 271 struct device *dev; 272 void *cookie; 273 int level; 274 int (*handler) __P((void *)); 275 void *arg; 276{ 277 unsigned mask; 278 279 switch ((int)cookie) { 280 /* slots 0-2 don't interrupt through the IOASIC. */ 281 case SYS_DEV_OPT0: 282 mask = MIPS_INT_MASK_0; 283 break; 284 case SYS_DEV_OPT1: 285 mask = MIPS_INT_MASK_1; 286 break; 287 case SYS_DEV_OPT2: 288 mask = MIPS_INT_MASK_2; 289 break; 290 291 case SYS_DEV_SCSI: 292 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 293 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 294 break; 295 case SYS_DEV_LANCE: 296 mask = KMIN_INTR_LANCE; 297 break; 298 case SYS_DEV_SCC0: 299 mask = KMIN_INTR_SCC_0; 300 break; 301 case SYS_DEV_SCC1: 302 mask = KMIN_INTR_SCC_1; 303 break; 304 default: 305#ifdef DIAGNOSTIC 306 printf("warning: enabling unknown intr %x\n", (int)cookie); 307#endif 308 return; 309 } 310 311#if defined(DEBUG) 312 printf("3MIN: imask %x, enabling slot %d, dev %p handler %p\n", 313 kmin_tc3_imask, (int)cookie, dev, handler); 314#endif 315 316 /* 317 * Enable the interrupt handler, and if it's an IOASIC 318 * slot, set the IOASIC interrupt mask. 319 * Otherwise, set the appropriate spl level in the R3000 320 * register. 321 * Be careful to set handlers before enabling, and disable 322 * interrupts before clearing handlers. 323 */ 324 325 /* Set the interrupt handler and argument ... */ 326 intrtab[(int)cookie].ih_func = handler; 327 intrtab[(int)cookie].ih_arg = arg; 328 /* ... and set the relevant mask */ 329 switch ((int)cookie) { 330 case SYS_DEV_OPT0: 331 case SYS_DEV_OPT1: 332 case SYS_DEV_OPT2: 333 /* it's an option slot */ 334 { 335 int s = splhigh(); 336 s |= mask; 337 splx(s); 338 } 339 break; 340 default: 341 /* it's a baseboard device going via the IOASIC */ 342 kmin_tc3_imask |= mask; 343 break; 344 } 345 346 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 347 kn02ba_wbflush(); 348} 349 350 351#define CHECKINTR(slot, bits) \ 352 do { \ 353 if (can_serve & (bits)) { \ 354 intrtab[slot].ih_count.ev_count++; \ 355 (*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \ 356 } \ 357 } while (0) 358 359static void 360dec_3min_intr(status, cause, pc, ipending) 361 unsigned status; 362 unsigned cause; 363 unsigned pc; 364 unsigned ipending; 365{ 366 static int user_warned = 0; 367 static int intr_depth = 0; 368 u_int32_t old_mask; 369 370 intr_depth++; 371 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 372 373 if (ipending & MIPS_INT_MASK_4) 374 prom_haltbutton(); 375 376 if (ipending & MIPS_INT_MASK_3) { 377 /* NB: status & MIPS_INT_MASK3 must also be set */ 378 /* masked interrupts are still observable */ 379 u_int32_t intr, imsk, can_serve, turnoff; 380 381 turnoff = 0; 382 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 383 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 384 can_serve = intr & imsk; 385 386 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 387 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 388#ifdef notdef 389 asc_dma_intr(); 390#endif 391 } 392 393 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 394 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 395 396 if (intr & IOASIC_INTR_LANCE_READ_E) 397 turnoff |= IOASIC_INTR_LANCE_READ_E; 398 399 if (turnoff) 400 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 401 402 if (intr & KMIN_INTR_TIMEOUT) { 403 kn02ba_errintr(); 404 pmax_memerr_evcnt.ev_count++; 405 } 406 407 if (intr & KMIN_INTR_CLOCK) { 408 struct clockframe cf; 409 410 __asm volatile("lbu $0,48(%0)" :: 411 "r"(ioasic_base + IOASIC_SLOT_8_START)); 412#ifdef MIPS3 413 if (CPUISMIPS3) { 414 latched_cycle_cnt = mips3_cp0_count_read(); 415 } 416#endif 417 cf.pc = pc; 418 cf.sr = status; 419 hardclock(&cf); 420 pmax_clock_evcnt.ev_count++; 421 } 422 423 /* If clock interrupts were enabled, re-enable them ASAP. */ 424 if (old_mask & KMIN_INTR_CLOCK) { 425 /* ioctl interrupt mask to splclock and higher */ 426 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 427 = old_mask & 428 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 429 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 430 kn02ba_wbflush(); 431 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 432 } 433 434 if (intr_depth > 1) 435 goto done; 436 437 CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); 438 CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1); 439 440#ifdef notyet /* untested */ 441 /* If tty interrupts were enabled, re-enable them ASAP. */ 442 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 443 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 444 *imaskp = old_mask & 445 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 446 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 447 kn02ba_wbflush(); 448 } 449 450 /* XXX until we know about SPLs of TC options. */ 451 if (intr_depth > 1) 452 goto done; 453#endif 454 CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE); 455 CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI); 456 457 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 458 printf("%s\n", "Power supply ok now."); 459 user_warned = 0; 460 } 461 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 462 user_warned++; 463 printf("%s\n", "Power supply overheating"); 464 } 465 } 466 if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) { 467 (*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg); 468 intrtab[SYS_DEV_OPT0].ih_count.ev_count++; 469 } 470 471 if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) { 472 (*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg); 473 intrtab[SYS_DEV_OPT1].ih_count.ev_count++; 474 } 475 if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) { 476 (*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg); 477 intrtab[SYS_DEV_OPT2].ih_count.ev_count++; 478 } 479 480done: 481 /* restore entry state */ 482 splhigh(); 483 intr_depth--; 484 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 485 486 _splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 487} 488 489 490 491/* 492 ************************************************************************ 493 * Extra functions 494 ************************************************************************ 495 */ 496 497static void 498kn02ba_wbflush() 499{ 500 /* read twice IOASIC_IMSK */ 501 __asm volatile("lw $0,%0; lw $0,%0" :: 502 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 503} 504 505static unsigned 506kn02ba_clkread() 507{ 508#ifdef MIPS3 509 if (CPUISMIPS3) { 510 u_int32_t mips3_cycles; 511 512 mips3_cycles = mips3_cp0_count_read() - latched_cycle_cnt; 513 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 514 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 515 (mips3_cycles >> 11)); 516 } 517#endif 518 return 0; 519} 520