exception_vector.S revision 1.1
1/* $NetBSD: exception_vector.S,v 1.1 2002/02/24 18:19:43 uch Exp $ */ 2 3/*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36#include "assym.h" 37 38#include <sh3/asm.h> 39#include <sh3/locore.h> 40 41/* 42 * Exception vectors. following routines are copied to vector addreses. 43 * sh_vector_generic: VBR + 0x100 44 * sh_vector_tlbmiss: VBR + 0x400 45 * sh_vector_interrupt: VBR + 0x600 46 */ 47 48/* 49 * void sh_vector_generic(void) __attribute__((__noreturn__)): 50 * copied to VBR+0x100. This code should be relocatable and max 384 51 * instructions. 52 * 0x40 TLB miss (load) 53 * 0x60 TLB miss (store) 54 * 0xc0 TLB protection (store) 55 * -> tlbmiss_exp() 56 * 0xa0 TLB protection (load) 57 * 0x80 Initial page write. 58 * and other... 59 * -> trap() 60 */ 61 .globl _C_LABEL(sh_vector_generic), _C_LABEL(sh_vector_generic_end) 62 .align 2 63_C_LABEL(sh_vector_generic): 64 EXCEPTION_ENTRY 65 /* Identify exception cause */ 66 MOV (EXPEVT, r0) 67 mov.l @r0, r0 68 /* 69 * TLB exception. 70 */ 71 cmp/eq #0x40, r0 /* T_TLBINVALIDR */ 72 bf 1f 733: 74 __INTR_MASK_r0_r1 75 __EXCEPTION_UNBLOCK_r0_r1 76 mov.l _L.tlb_handler, r0 77 jsr @r0 78 nop 79 bra 4f 80 nop 811: 82 cmp/eq #0x60, r0 /* T_TLBINVALIDW */ 83 bt 3b 84 85 mov.l _L.TLBPROTWR, r1 /* T_TLBPRIVW */ 86 cmp/eq r0, r1 87 bt 3b 88 89 /* 90 * General exception. 91 */ 92#ifdef DDB 93 mov #0, r2 94 MOV (BBRA, r1) 95 mov.w r2, @r1 /* disable UBC */ 96 mov.l r2, @(TF_UBC, r15) /* clear trapframe->tf_ubc */ 97#endif /* DDB */ 98 99 mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = EXPEVT */ 100 __INTR_UNMASK_r0_r1 101 __EXCEPTION_UNBLOCK_r0_r1 102 mov.l _L.trap, r0 103 jsr @r0 104 mov r15, r4 105 106 /* Check for ASTs on exit to user mode. */ 107 mov.l _L.ast, r0 108 jsr @r0 109 mov r15, r4 110 111#ifdef DDB /* BBRA = trapframe->tf_ubc */ 112 __EXCEPTION_BLOCK_r0_r1 113 mov.l @(TF_UBC, r15), r0 114 MOV (BBRA, r1) 115 mov.w r0, @r1 116#endif /* DDB */ 1174: 118 EXCEPTION_RETURN 119 /* NOTREACHED */ 120 .align 2 121REG_SYMBOL(EXPEVT) 122REG_SYMBOL(BBRA) 123_L.TLBPROTWR: .long 0x000000c0 124_L.trap: .long _C_LABEL(trap) 125_L.ast: .long _C_LABEL(ast) 126_L.tlb_handler: .long _C_LABEL(tlb_handler) 127_C_LABEL(sh_vector_generic_end): 128 129/* 130 * void sh_vector_tlbmiss(void) __attribute__((__noreturn__)): 131 * copied to VBR+0x400. This code should be relocatable and max 256 132 * instructions. 133 */ 134 .globl _C_LABEL(sh_vector_tlbmiss), _C_LABEL(sh_vector_tlbmiss_end) 135 .align 2 136_C_LABEL(sh_vector_tlbmiss): 137 EXCEPTION_ENTRY 138 __INTR_MASK_r0_r1 139 __EXCEPTION_UNBLOCK_r0_r1 140 mov.l 1f, r0 141 jsr @r0 142 nop 143 EXCEPTION_RETURN 144 .align 2 1451: .long _C_LABEL(tlb_handler) 146_C_LABEL(sh_vector_tlbmiss_end): 147 148 149/* 150 * void sh_vector_interrupt(void) __attribute__((__noreturn__)): 151 * copied to VBR+0x600. This code should be relocatable. 152 */ 153 .globl _C_LABEL(sh_vector_interrupt), _C_LABEL(sh_vector_interrupt_end) 154 .align 2 155_C_LABEL(sh_vector_interrupt): 156 EXCEPTION_ENTRY 157 mov.l 1f, r0 158 jmp @r0 159 nop 160 .align 2 1611: .long _C_LABEL(interrupt_exp) 162_C_LABEL(sh_vector_interrupt_end): 163 164