exception_vector.S revision 1.2
1/* $NetBSD: exception_vector.S,v 1.2 2002/02/28 01:53:43 uch Exp $ */ 2 3/*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36#include "assym.h" 37 38#include <sh3/asm.h> 39#include <sh3/locore.h> 40#include <sh3/trapreg.h> 41#include <sh3/ubcreg.h> 42 43/* 44 * Exception vectors. following routines are copied to vector addreses. 45 * sh_vector_generic: VBR + 0x100 46 * sh_vector_tlbmiss: VBR + 0x400 47 * sh_vector_interrupt: VBR + 0x600 48 */ 49 50/* 51 * void sh_vector_generic(void) __attribute__((__noreturn__)): 52 * copied to VBR+0x100. This code should be relocatable and max 384 53 * instructions. 54 * 0x40 TLB miss (load) 55 * 0x60 TLB miss (store) 56 * 0xc0 TLB protection (store) 57 * -> tlbmiss_exp() 58 * 0xa0 TLB protection (load) 59 * 0x80 Initial page write. 60 * and other... 61 * -> trap() 62 */ 63 .globl _C_LABEL(sh_vector_generic), _C_LABEL(sh_vector_generic_end) 64 .align 2 65_C_LABEL(sh_vector_generic): 66 EXCEPTION_ENTRY 67 /* Identify exception cause */ 68 MOV (EXPEVT, r0) 69 mov.l @r0, r0 70 /* 71 * TLB exception. 72 */ 73 cmp/eq #0x40, r0 /* T_TLBINVALIDR */ 74 bf 1f 753: 76 __INTR_MASK(r0, r1) 77 __EXCEPTION_UNBLOCK(r0, r1) 78 mov.l _L.tlb_handler, r0 79 jsr @r0 80 nop 81 bra 4f 82 nop 831: 84 cmp/eq #0x60, r0 /* T_TLBINVALIDW */ 85 bt 3b 86 87 mov.l _L.TLBPROTWR, r1 /* T_TLBPRIVW */ 88 cmp/eq r0, r1 89 bt 3b 90 91 /* 92 * General exception. 93 */ 94#ifdef DDB 95 mov #0, r2 96 MOV (BBRA, r1) 97 mov.w r2, @r1 /* disable UBC */ 98 mov.l r2, @(TF_UBC, r15) /* clear trapframe->tf_ubc */ 99#endif /* DDB */ 100 101 mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = EXPEVT */ 102 __INTR_UNMASK(r0, r1) 103 __EXCEPTION_UNBLOCK(r0, r1) 104 mov.l _L.trap, r0 105 jsr @r0 106 mov r15, r4 107 108 /* Check for ASTs on exit to user mode. */ 109 mov.l _L.ast, r0 110 jsr @r0 111 mov r15, r4 112 113#ifdef DDB /* BBRA = trapframe->tf_ubc */ 114 __EXCEPTION_BLOCK(r0, r1) 115 mov.l @(TF_UBC, r15), r0 116 MOV (BBRA, r1) 117 mov.w r0, @r1 118#endif /* DDB */ 1194: 120 EXCEPTION_RETURN 121 /* NOTREACHED */ 122 .align 2 123REG_SYMBOL(EXPEVT) 124REG_SYMBOL(BBRA) 125_L.TLBPROTWR: .long 0x000000c0 126_L.trap: .long _C_LABEL(trap) 127_L.ast: .long _C_LABEL(ast) 128_L.tlb_handler: .long _C_LABEL(tlb_handler) 129_C_LABEL(sh_vector_generic_end): 130 131/* 132 * void sh_vector_tlbmiss(void) __attribute__((__noreturn__)): 133 * copied to VBR+0x400. This code should be relocatable and max 256 134 * instructions. 135 */ 136 .globl _C_LABEL(sh_vector_tlbmiss), _C_LABEL(sh_vector_tlbmiss_end) 137 .align 2 138_C_LABEL(sh_vector_tlbmiss): 139 EXCEPTION_ENTRY 140 __INTR_MASK(r0, r1) 141 __EXCEPTION_UNBLOCK(r0, r1) 142 mov.l 1f, r0 143 jsr @r0 144 nop 145 EXCEPTION_RETURN 146 .align 2 1471: .long _C_LABEL(tlb_handler) 148_C_LABEL(sh_vector_tlbmiss_end): 149 150 151/* 152 * void sh_vector_interrupt(void) __attribute__((__noreturn__)): 153 * copied to VBR+0x600. This code should be relocatable. 154 */ 155 .globl _C_LABEL(sh_vector_interrupt), _C_LABEL(sh_vector_interrupt_end) 156 .align 2 157_C_LABEL(sh_vector_interrupt): 158 EXCEPTION_ENTRY 159 mov.l 1f, r0 160 jmp @r0 161 nop 162 .align 2 1631: .long _C_LABEL(interrupt_exp) 164_C_LABEL(sh_vector_interrupt_end): 165 166