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schizo.c revision 1.31
      1 /*	$NetBSD: schizo.c,v 1.30 2012/10/27 17:18:12 chs Exp $	*/
      2 /*	$OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $	*/
      3 
      4 /*
      5  * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net)
      6  * Copyright (c) 2003 Henric Jungheim
      7  * Copyright (c) 2008, 2009, 2010, 2012 Matthew R. Green
      8  * All rights reserved.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     22  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     28  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.30 2012/10/27 17:18:12 chs Exp $");
     34 
     35 #include <sys/param.h>
     36 #include <sys/device.h>
     37 #include <sys/errno.h>
     38 #include <sys/extent.h>
     39 #include <sys/kmem.h>
     40 #include <sys/malloc.h>
     41 #include <sys/systm.h>
     42 #include <sys/time.h>
     43 #include <sys/reboot.h>
     44 
     45 #define _SPARC_BUS_DMA_PRIVATE
     46 #include <sys/bus.h>
     47 #include <machine/autoconf.h>
     48 #include <machine/psl.h>
     49 
     50 #include <dev/pci/pcivar.h>
     51 #include <dev/pci/pcireg.h>
     52 
     53 #include <sparc64/dev/iommureg.h>
     54 #include <sparc64/dev/iommuvar.h>
     55 #include <sparc64/dev/schizoreg.h>
     56 #include <sparc64/dev/schizovar.h>
     57 #include <sparc64/sparc64/cache.h>
     58 
     59 #ifdef DEBUG
     60 #define SDB_PROM        0x01
     61 #define SDB_BUSMAP      0x02
     62 #define SDB_INTR        0x04
     63 #define SDB_INTMAP      0x08
     64 #define SDB_CONF        0x10
     65 int schizo_debug = 0x0;
     66 #define DPRINTF(l, s)   do { if (schizo_debug & l) printf s; } while (0)
     67 #else
     68 #define DPRINTF(l, s)
     69 #endif
     70 
     71 extern struct sparc_pci_chipset _sparc_pci_chipset;
     72 
     73 static	int	schizo_match(device_t, cfdata_t, void *);
     74 static	void	schizo_attach(device_t, device_t, void *);
     75 static	int	schizo_print(void *aux, const char *p);
     76 
     77 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc),
     78     schizo_match, schizo_attach, NULL, NULL);
     79 
     80 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *);
     81 
     82 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int,
     83     int (*handler)(void *), void *, int, const char *);
     84 int schizo_ue(void *);
     85 int schizo_ce(void *);
     86 int schizo_safari_error(void *);
     87 int schizo_pci_error(void *);
     88 
     89 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int,
     90     pci_chipset_tag_t);
     91 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *);
     92 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *);
     93 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *);
     94 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *,
     95     int);
     96 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *);
     97 
     98 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int);
     99 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
    100 
    101 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size,
    102 	           int flags, vaddr_t unused, bus_space_handle_t *hp);
    103 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr,
    104                                off_t off, int prot, int flags);
    105 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *),
    106 	void *, void(*)(void));
    107 static int schizo_pci_intr_map(const struct pci_attach_args *,
    108     pci_intr_handle_t *);
    109 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
    110                                        int, int (*)(void *), void *);
    111 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
    112 	bus_size_t, int, bus_dmamap_t *);
    113 
    114 int
    115 schizo_match(device_t parent, cfdata_t match, void *aux)
    116 {
    117 	struct mainbus_attach_args *ma = aux;
    118 	char *str;
    119 
    120 	if (strcmp(ma->ma_name, "pci") != 0)
    121 		return (0);
    122 
    123 	str = prom_getpropstring(ma->ma_node, "model");
    124 	if (strcmp(str, "schizo") == 0)
    125 		return (1);
    126 
    127 	str = prom_getpropstring(ma->ma_node, "compatible");
    128 	if (strcmp(str, "pci108e,8001") == 0)
    129 		return (1);
    130 	if (strcmp(str, "pci108e,8002") == 0)		/* XMITS */
    131 		return (1);
    132 	if (strcmp(str, "pci108e,a801") == 0)		/* Tomatillo */
    133 		return (1);
    134 
    135 	return (0);
    136 }
    137 
    138 void
    139 schizo_attach(device_t parent, device_t self, void *aux)
    140 {
    141 	struct schizo_softc *sc = device_private(self);
    142 	struct mainbus_attach_args *ma = aux;
    143 	struct schizo_pbm *pbm;
    144 	struct iommu_state *is;
    145 	struct pcibus_attach_args pba;
    146 	uint64_t reg, eccctrl;
    147 	int *busranges = NULL, nranges;
    148 	char *str;
    149 	bool no_sc;
    150 
    151 	aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr);
    152 	str = prom_getpropstring(ma->ma_node, "compatible");
    153 	if (strcmp(str, "pci108e,a801") == 0)
    154 		sc->sc_tomatillo = 1;
    155 
    156 	sc->sc_ver = prom_getpropint(sc->sc_node, "version#", 0);
    157 
    158 	sc->sc_dev = self;
    159 	sc->sc_node = ma->ma_node;
    160 	sc->sc_dmat = ma->ma_dmatag;
    161 	sc->sc_bustag = ma->ma_bustag;
    162 
    163 	if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL,
    164 	    sizeof(struct schizo_regs), 0,
    165 	    &sc->sc_ctrlh)) {
    166 		aprint_error(": failed to map registers\n");
    167 		return;
    168 	}
    169 
    170 	sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT);
    171 
    172 	/* enable schizo ecc error interrupts */
    173 	eccctrl = schizo_read(sc, SCZ_ECCCTRL);
    174 	eccctrl |= SCZ_ECCCTRL_EE_INTEN |
    175 		   SCZ_ECCCTRL_UE_INTEN |
    176 		   SCZ_ECCCTRL_CE_INTEN;
    177 	schizo_write(sc, SCZ_ECCCTRL, eccctrl);
    178 
    179 	pbm = kmem_zalloc(sizeof(*pbm), KM_NOSLEEP);
    180 	if (pbm == NULL)
    181 		panic("schizo: can't alloc schizo pbm");
    182 
    183 	pbm->sp_sc = sc;
    184 	pbm->sp_regt = sc->sc_bustag;
    185 
    186 	if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000)
    187 		pbm->sp_bus_a = 1;
    188 	else
    189 		pbm->sp_bus_a = 0;
    190 
    191 	/*
    192 	 * Map interrupt registers
    193 	 */
    194 	if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr,
    195 			  ma->ma_reg[0].ur_len,
    196 			  BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) {
    197 		aprint_error(": failed to interrupt map registers\n");
    198 		return;
    199 	}
    200 
    201 	if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range),
    202 	    &pbm->sp_nrange, (void **)&pbm->sp_range))
    203 		panic("schizo: can't get ranges");
    204 
    205 	if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges,
    206 	    (void **)&busranges))
    207 		panic("schizo: can't get bus-range");
    208 
    209 	aprint_normal(": \"%s\", version %d, ign %x, bus %c %d to %d\n",
    210 	    sc->sc_tomatillo ? "Tomatillo" : "Schizo", sc->sc_ver,
    211 	    sc->sc_ign, pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]);
    212 	aprint_naive("\n");
    213 
    214 	if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh,
    215 	    pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) :
    216 	    offsetof(struct schizo_regs, pbm_b),
    217 	    sizeof(struct schizo_pbm_regs),
    218 	    &pbm->sp_regh)) {
    219 		panic("schizo: unable to create PBM handle");
    220 	}
    221 
    222 	is = &pbm->sp_is;
    223 	pbm->sp_sb.sb_is = is;
    224 	no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0;
    225 	if (no_sc)
    226 		aprint_debug_dev(sc->sc_dev, "no streaming buffers\n");
    227 	else {
    228 		vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40];
    229 
    230 		/*
    231 		 * Initialize the strbuf_ctl.
    232 		 *
    233 		 * The flush sync buffer must be 64-byte aligned.
    234 		 */
    235 		is->is_sb[0] = &pbm->sp_sb;
    236 		is->is_sb[0]->sb_flush = (void *)(va & ~0x3f);
    237 
    238 		bus_space_subregion(pbm->sp_regt, pbm->sp_regh,
    239 			offsetof(struct schizo_pbm_regs, strbuf),
    240 			sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb);
    241 	}
    242 
    243 	aprint_normal_dev(sc->sc_dev, " ");
    244 	schizo_init_iommu(sc, pbm);
    245 
    246 	pbm->sp_memt = schizo_alloc_mem_tag(pbm);
    247 	pbm->sp_iot = schizo_alloc_io_tag(pbm);
    248 	pbm->sp_cfgt = schizo_alloc_config_tag(pbm);
    249 	pbm->sp_dmat = schizo_alloc_dma_tag(pbm);
    250 	pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) |
    251 		        (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0);
    252 
    253 	if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh))
    254 		panic("schizo: could not map config space");
    255 
    256 	pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node,
    257 	    &_sparc_pci_chipset);
    258 	pbm->sp_pc->spc_busmax = busranges[1];
    259 	pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode),
    260 	    KM_NOSLEEP);
    261 	if (pbm->sp_pc->spc_busnode == NULL)
    262 		panic("schizo: kmem_alloc busnode");
    263 
    264 	pba.pba_bus = busranges[0];
    265 	pba.pba_bridgetag = NULL;
    266 	pba.pba_pc = pbm->sp_pc;
    267 	pba.pba_flags = pbm->sp_flags;
    268 	pba.pba_dmat = pbm->sp_dmat;
    269 	pba.pba_dmat64 = NULL;	/* XXX */
    270 	pba.pba_memt = pbm->sp_memt;
    271 	pba.pba_iot = pbm->sp_iot;
    272 
    273 	free(busranges, M_DEVBUF);
    274 
    275 	schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5);
    276 
    277 	/* clear out the bus errors */
    278 	schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL));
    279 	schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR));
    280 	schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG,
    281 	    schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG));
    282 
    283 	reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL);
    284 	/* enable/disable error interrupts and arbiter */
    285 	reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT;
    286 	if (sc->sc_tomatillo) {
    287 		reg &= ~SCZ_PCICTRL_SBH_INT;
    288 		reg |= TOM_PCICTRL_ARB;
    289 		reg |= TOM_PCICTRL_PRM | TOM_PCICTRL_PRO |
    290 		       TOM_PCICTRL_PRL;
    291 		if (sc->sc_ver <= 1)	/* 2.0 */
    292 			reg |= TOM_PCICTRL_DTO_INT;
    293 		else
    294 			reg |= SCZ_PCICTRL_PTO;
    295 	} else
    296 		reg |= SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_ARB;
    297 	if (OF_getproplen(sc->sc_node, "no-bus-parking") < 0)
    298 		reg |= SCZ_PCICTRL_PARK;
    299 	schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg);
    300 
    301 	reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG);
    302 	reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY |
    303 	    SCZ_PCIDIAG_D_INTSYNC);
    304 	schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg);
    305 
    306 	if (pbm->sp_bus_a)
    307 		schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
    308 		   pbm, SCZ_PCIERR_A_INO, "pci_a");
    309 	else
    310 		schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
    311 		   pbm, SCZ_PCIERR_B_INO, "pci_b");
    312 
    313 	/* double mapped */
    314 	schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO,
    315 	    "ue");
    316 	schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO,
    317 	    "ce");
    318 	schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc,
    319 	    SCZ_SERR_INO, "safari");
    320 
    321 	if (sc->sc_tomatillo) {
    322 		/*
    323 		 * Enable the IOCACHE.
    324 		 */
    325 		uint64_t iocache_csr;
    326 
    327 		iocache_csr = TOM_IOCACHE_CSR_WRT_PEN |
    328 			      (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) |
    329 			      TOM_IOCACHE_CSR_PEN_RDM |
    330 			      TOM_IOCACHE_CSR_PEN_ONE |
    331 			      TOM_IOCACHE_CSR_PEN_LINE;
    332 		schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr);
    333 	}
    334 
    335 	config_found(sc->sc_dev, &pba, schizo_print);
    336 }
    337 
    338 int
    339 schizo_ue(void *vsc)
    340 {
    341 	struct schizo_softc *sc = vsc;
    342 
    343 	panic("%s: uncorrectable error", device_xname(sc->sc_dev));
    344 	return (1);
    345 }
    346 
    347 int
    348 schizo_ce(void *vsc)
    349 {
    350 	struct schizo_softc *sc = vsc;
    351 
    352 	panic("%s: correctable error", device_xname(sc->sc_dev));
    353 	return (1);
    354 }
    355 
    356 int
    357 schizo_pci_error(void *vpbm)
    358 {
    359 	struct schizo_pbm *sp = vpbm;
    360 	struct schizo_softc *sc = sp->sp_sc;
    361 	u_int64_t afsr, afar, ctrl, tfar;
    362 	u_int32_t csr;
    363 	char bits[128];
    364 
    365 	afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR);
    366 	afar = schizo_pbm_read(sp, SCZ_PCI_AFAR);
    367 	ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL);
    368 	csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG);
    369 
    370 	printf("%s: pci bus %c error\n", device_xname(sc->sc_dev),
    371 	    sp->sp_bus_a ? 'A' : 'B');
    372 
    373 	snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr);
    374 	printf("PCIAFSR=%s\n", bits);
    375 	printf("PCIAFAR=%" PRIx64 "\n", afar);
    376 	snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl);
    377 	printf("PCICTRL=%s\n", bits);
    378 #ifdef PCI_COMMAND_STATUS_BITS
    379 	snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr);
    380 	printf("PCICSR=%s\n", bits);
    381 #endif
    382 
    383 	if (ctrl & SCZ_PCICTRL_MMU_ERR) {
    384 		ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL);
    385 		printf("IOMMUCTRL=%" PRIx64 "\n", ctrl);
    386 
    387 		if ((ctrl & TOM_IOMMU_ERR) == 0)
    388 			goto clear_error;
    389 
    390 		if (sc->sc_tomatillo) {
    391 			tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR);
    392 			printf("IOMMUTFAR=%" PRIx64 "\n", tfar);
    393 		}
    394 
    395 		/* These are non-fatal if target abort was signalled. */
    396 		if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR ||
    397 		    ctrl & TOM_IOMMU_ILLTSBTBW_ERR ||
    398 		    ctrl & TOM_IOMMU_BADVA_ERR) {
    399 			if (csr & PCI_STATUS_TARGET_TARGET_ABORT) {
    400 				schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl);
    401 				goto clear_error;
    402 			}
    403 		}
    404 	}
    405 
    406 	panic("%s: fatal", device_xname(sc->sc_dev));
    407 
    408  clear_error:
    409 	schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr);
    410 	schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl);
    411 	schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr);
    412 	return (1);
    413 }
    414 
    415 int
    416 schizo_safari_error(void *vsc)
    417 {
    418 	struct schizo_softc *sc = vsc;
    419 
    420 	printf("%s: safari error\n", device_xname(sc->sc_dev));
    421 
    422 	printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG));
    423 	printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR));
    424 	printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR));
    425 	printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR));
    426 	printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR));
    427 
    428 	panic("%s: fatal", device_xname(sc->sc_dev));
    429 	return (1);
    430 }
    431 
    432 void
    433 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm)
    434 {
    435 	struct iommu_state *is = &pbm->sp_is;
    436 	int *vdma = NULL, nitem, tsbsize = 7;
    437 	u_int32_t iobase = -1;
    438 	char *name;
    439 
    440 	/* punch in our copies */
    441 	is->is_bustag = pbm->sp_regt;
    442 	bus_space_subregion(is->is_bustag, pbm->sp_regh,
    443 		offsetof(struct schizo_pbm_regs, iommu),
    444 		sizeof(struct iommureg2),
    445 		&is->is_iommu);
    446 
    447 	/*
    448 	 * Separate the men from the boys.  If the `virtual-dma'
    449 	 * property exists, use it.
    450 	 */
    451 	if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem,
    452 	    (void **)&vdma)) {
    453 		/* Damn.  Gotta use these values. */
    454 		iobase = vdma[0];
    455 #define	TSBCASE(x)	case 1 << ((x) + 23): tsbsize = (x); break
    456 		switch (vdma[1]) {
    457 			TSBCASE(1); TSBCASE(2); TSBCASE(3);
    458 			TSBCASE(4); TSBCASE(5); TSBCASE(6);
    459 		default:
    460 			printf("bogus tsb size %x, using 7\n", vdma[1]);
    461 			TSBCASE(7);
    462 		}
    463 #undef TSBCASE
    464 		DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase));
    465 		free(vdma, M_DEVBUF);
    466 	} else {
    467 		DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, "
    468 		    "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize));
    469 	}
    470 
    471 	/* give us a nice name.. */
    472 	name = (char *)kmem_alloc(32, KM_NOSLEEP);
    473 	if (name == NULL)
    474 
    475 		panic("couldn't kmem_alloc iommu name");
    476 	snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev));
    477 
    478 	iommu_init(name, is, tsbsize, iobase);
    479 }
    480 
    481 int
    482 schizo_print(void *aux, const char *p)
    483 {
    484 
    485 	if (p == NULL)
    486 		return (UNCONF);
    487 	return (QUIET);
    488 }
    489 
    490 pcireg_t
    491 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
    492 {
    493 	struct schizo_pbm *sp = pc->cookie;
    494 	struct cpu_info *ci = curcpu();
    495 	pcireg_t val = (pcireg_t)~0;
    496 	int s;
    497 
    498 	DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg));
    499 	if (PCITAG_NODE(tag) != -1) {
    500 		s = splhigh();
    501 		ci->ci_pci_probe = true;
    502 		membar_Sync();
    503 		val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh,
    504 		    PCITAG_OFFSET(tag) + reg);
    505 		membar_Sync();
    506 		if (ci->ci_pci_fault)
    507 			val = (pcireg_t)~0;
    508 		ci->ci_pci_probe = ci->ci_pci_fault = false;
    509 		splx(s);
    510 	}
    511 	DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val));
    512 	return (val);
    513 }
    514 
    515 void
    516 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
    517 {
    518 	struct schizo_pbm *sp = pc->cookie;
    519 
    520 	DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__,
    521 		(long)tag, reg, (int)data));
    522 
    523 	/* If we don't know it, just punt it.  */
    524 	if (PCITAG_NODE(tag) == -1) {
    525 		DPRINTF(SDB_CONF, (" .. bad addr\n"));
    526 		return;
    527 	}
    528 
    529         bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh,
    530 	    PCITAG_OFFSET(tag) + reg, data);
    531 	DPRINTF(SDB_CONF, (" .. done\n"));
    532 }
    533 
    534 void
    535 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl,
    536     int (*handler)(void *), void *arg, int ino, const char *what)
    537 {
    538 	struct intrhand *ih;
    539 	u_int64_t mapoff, clroff;
    540 	uintptr_t intrregs;
    541 
    542 	DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__,
    543 	    ino, sc->sc_ign, handler, arg));
    544 
    545 	mapoff = offsetof(struct schizo_pbm_regs, imap[ino]);
    546 	clroff = offsetof(struct schizo_pbm_regs, iclr[ino]);
    547 	ino |= sc->sc_ign;
    548 
    549 	DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n",
    550 	    mapoff, clroff));
    551 
    552 	ih = (struct intrhand *)
    553 		kmem_alloc(sizeof(struct intrhand), KM_NOSLEEP);
    554 	if (ih == NULL)
    555 		return;
    556 	ih->ih_arg = arg;
    557 	intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh);
    558 	ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff);
    559 	ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff);
    560 	ih->ih_fun = handler;
    561 	ih->ih_pil = ipl;
    562 	ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff));
    563 	ih->ih_pending = 0;
    564 
    565 	intr_establish(ipl, ipl != IPL_VM, ih);
    566 
    567 	schizo_pbm_write(pbm, mapoff,
    568 	    ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT));
    569 }
    570 
    571 bus_space_tag_t
    572 schizo_alloc_mem_tag(struct schizo_pbm *sp)
    573 {
    574 	return (schizo_alloc_bus_tag(sp, "mem", PCI_MEMORY_BUS_SPACE));
    575 }
    576 
    577 bus_space_tag_t
    578 schizo_alloc_io_tag(struct schizo_pbm *sp)
    579 {
    580 	return (schizo_alloc_bus_tag(sp, "io", PCI_IO_BUS_SPACE));
    581 }
    582 
    583 bus_space_tag_t
    584 schizo_alloc_config_tag(struct schizo_pbm *sp)
    585 {
    586 	return (schizo_alloc_bus_tag(sp, "cfg", PCI_CONFIG_BUS_SPACE));
    587 }
    588 
    589 bus_space_tag_t
    590 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type)
    591 {
    592 	struct schizo_softc *sc = pbm->sp_sc;
    593 	bus_space_tag_t bt;
    594 
    595 	bt = (bus_space_tag_t) kmem_zalloc(sizeof(struct sparc_bus_space_tag),
    596 		    KM_NOSLEEP);
    597 	if (bt == NULL)
    598 		panic("schizo: could not allocate bus tag");
    599 
    600 	bt->cookie = pbm;
    601 	bt->parent = sc->sc_bustag;
    602 	bt->type = type;
    603 	bt->sparc_bus_map = schizo_bus_map;
    604 	bt->sparc_bus_mmap = schizo_bus_mmap;
    605 	bt->sparc_intr_establish = schizo_intr_establish;
    606 	return (bt);
    607 }
    608 
    609 bus_dma_tag_t
    610 schizo_alloc_dma_tag(struct schizo_pbm *pbm)
    611 {
    612 	struct schizo_softc *sc = pbm->sp_sc;
    613 	bus_dma_tag_t dt, pdt = sc->sc_dmat;
    614 
    615 	dt = kmem_zalloc(sizeof(*dt), KM_NOSLEEP);
    616 	if (dt == NULL)
    617 		panic("schizo: could not alloc dma tag");
    618 
    619 	dt->_cookie = pbm;
    620 	dt->_parent = pdt;
    621 #define PCOPY(x)	dt->x = pdt->x
    622 	dt->_dmamap_create = schizo_dmamap_create;
    623 	PCOPY(_dmamap_destroy);
    624 	dt->_dmamap_load = iommu_dvmamap_load;
    625 	PCOPY(_dmamap_load_mbuf);
    626 	PCOPY(_dmamap_load_uio);
    627 	dt->_dmamap_load_raw = iommu_dvmamap_load_raw;
    628 	dt->_dmamap_unload = iommu_dvmamap_unload;
    629 	dt->_dmamap_sync = iommu_dvmamap_sync;
    630 	dt->_dmamem_alloc = iommu_dvmamem_alloc;
    631 	dt->_dmamem_free = iommu_dvmamem_free;
    632 	dt->_dmamem_map = iommu_dvmamem_map;
    633 	dt->_dmamem_unmap = iommu_dvmamem_unmap;
    634 	PCOPY(_dmamem_mmap);
    635 #undef	PCOPY
    636 	return (dt);
    637 }
    638 
    639 pci_chipset_tag_t
    640 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc)
    641 {
    642 	pci_chipset_tag_t npc;
    643 
    644 	npc = kmem_alloc(sizeof *npc, KM_NOSLEEP);
    645 	if (npc == NULL)
    646 		panic("schizo: could not allocate pci_chipset_tag_t");
    647 	memcpy(npc, pc, sizeof *pc);
    648 	npc->cookie = pbm;
    649 	npc->rootnode = node;
    650 	npc->spc_conf_read = schizo_conf_read;
    651 	npc->spc_conf_write = schizo_conf_write;
    652 	npc->spc_intr_map = schizo_pci_intr_map;
    653 	npc->spc_intr_establish = schizo_pci_intr_establish;
    654 	npc->spc_find_ino = NULL;
    655 	return (npc);
    656 }
    657 
    658 int
    659 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size,
    660     int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags,
    661     bus_dmamap_t *dmamp)
    662 {
    663 	struct schizo_pbm *pbm = t->_cookie;
    664 	int error;
    665 
    666 	error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
    667 				  boundary, flags, dmamp);
    668 	if (error == 0)
    669 		(*dmamp)->_dm_cookie = &pbm->sp_sb;
    670 	return error;
    671 }
    672 
    673 static struct schizo_range *
    674 get_schizorange(struct schizo_pbm *pbm, int ss)
    675 {
    676 	int i;
    677 
    678 	for (i = 0; i < pbm->sp_nrange; i++) {
    679 		if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss)
    680 			return (&pbm->sp_range[i]);
    681 	}
    682 	/* not found */
    683 	return (NULL);
    684 }
    685 
    686 int
    687 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size,
    688 	       int flags, vaddr_t unused, bus_space_handle_t *hp)
    689 {
    690 	bus_addr_t paddr;
    691 	struct schizo_pbm *pbm = t->cookie;
    692 	struct schizo_softc *sc = pbm->sp_sc;
    693 	struct schizo_range *sr;
    694 	int ss;
    695 
    696 	DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d",
    697 	    t->type,
    698 	    (unsigned long long)offset,
    699 	    (unsigned long long)size,
    700 	    flags));
    701 
    702 	ss = sparc_pci_childspace(t->type);
    703 	DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss));
    704 
    705 	sr = get_schizorange(pbm, ss);
    706 	if (sr != NULL) {
    707 		paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset);
    708 		DPRINTF(SDB_BUSMAP, ("%s: mapping paddr "
    709 				     "space %lx offset %lx paddr %qx\n",
    710 			       __func__, (long)ss, (long)offset,
    711 			       (unsigned long long)paddr));
    712 		return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size,
    713 			flags, 0, hp));
    714 	}
    715 	DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__));
    716 	return (EINVAL);
    717 }
    718 
    719 static paddr_t
    720 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot,
    721 	int flags)
    722 {
    723 	bus_addr_t offset = paddr;
    724 	struct schizo_pbm *pbm = t->cookie;
    725 	struct schizo_softc *sc = pbm->sp_sc;
    726 	struct schizo_range *sr;
    727 	int ss;
    728 
    729 	ss = sparc_pci_childspace(t->type);
    730 
    731 	DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n",
    732 	    prot, flags, (unsigned long long)paddr));
    733 
    734 	sr = get_schizorange(pbm, ss);
    735 	if (sr != NULL) {
    736 		paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset);
    737 		DPRINTF(SDB_BUSMAP, ("%s: mapping paddr "
    738 				     "space %lx offset %lx paddr %qx\n",
    739 			       __func__, (long)ss, (long)offset,
    740 			       (unsigned long long)paddr));
    741 		return (bus_space_mmap(sc->sc_bustag, paddr, off,
    742 				       prot, flags));
    743 	}
    744 	DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__));
    745 	return (-1);
    746 }
    747 
    748 /*
    749  * Set the IGN for this schizo into the handle.
    750  */
    751 int
    752 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
    753 {
    754 	struct schizo_pbm *pbm = pa->pa_pc->cookie;
    755 	struct schizo_softc *sc = pbm->sp_sc;
    756 
    757 	*ihp |= sc->sc_ign;
    758 	DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp));
    759 	return (0);
    760 }
    761 
    762 static void *
    763 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level,
    764 	int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */)
    765 {
    766 	struct schizo_pbm *pbm = t->cookie;
    767 	struct intrhand *ih = NULL;
    768 	uint64_t mapoff, clroff;
    769 	uintptr_t intrregs;
    770 	volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL;
    771 	int ino;
    772 	long vec;
    773 
    774 	vec = INTVEC(ihandle);
    775 	ino = INTINO(vec);
    776 
    777 	ih = kmem_alloc(sizeof *ih, KM_NOSLEEP);
    778 	if (ih == NULL)
    779 		return (NULL);
    780 
    781 	DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__,
    782 	    ihandle, level, handler, arg));
    783 
    784 	if (level == IPL_NONE)
    785 		level = INTLEV(vec);
    786 	if (level == IPL_NONE) {
    787 		printf(": no IPL, setting IPL 2.\n");
    788 		level = 2;
    789 	}
    790 
    791 	mapoff = offsetof(struct schizo_pbm_regs, imap[ino]);
    792 	clroff = offsetof(struct schizo_pbm_regs, iclr[ino]);
    793 
    794 	DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %"
    795 	    PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff));
    796 
    797 	ih->ih_ivec = ihandle;
    798 
    799 	intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh);
    800 	intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff);
    801 	intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff);
    802 
    803 	if (INTIGN(vec) == 0)
    804 		ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN;
    805 	else
    806 		ino |= vec & INTMAP_IGN;
    807 
    808 	/* Register the map and clear intr registers */
    809 	ih->ih_map = intrmapptr;
    810 	ih->ih_clr = intrclrptr;
    811 
    812 	ih->ih_fun = handler;
    813 	ih->ih_arg = arg;
    814 	ih->ih_pil = level;
    815 	ih->ih_number = ino;
    816 	ih->ih_pending = 0;
    817 
    818 	DPRINTF(SDB_INTR, (
    819 	    "; installing handler %p arg %p with inr %x pil %u\n",
    820 	    handler, arg, ino, (u_int)ih->ih_pil));
    821 
    822 	intr_establish(ih->ih_pil, level != IPL_VM, ih);
    823 
    824 	/*
    825 	 * Enable the interrupt now we have the handler installed.
    826 	 * Read the current value as we can't change it besides the
    827 	 * valid bit so so make sure only this bit is changed.
    828 	 */
    829 	if (intrmapptr) {
    830 		u_int64_t imap;
    831 
    832 		imap = schizo_pbm_readintr(pbm, mapoff);
    833 		DPRINTF(SDB_INTR, ("; read intrmap = %016qx",
    834 			(unsigned long long)imap));
    835 		imap |= INTMAP_V;
    836 		DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr));
    837 		DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n",
    838 			(unsigned long long)imap));
    839 		schizo_pbm_writeintr(pbm, mapoff, imap);
    840 		imap = schizo_pbm_readintr(pbm, mapoff);
    841 		DPRINTF(SDB_INTR, ("; reread intrmap = %016qx",
    842 			(unsigned long long)imap));
    843 		ih->ih_number |= imap & INTMAP_INR;
    844 	}
    845  	if (intrclrptr) {
    846  		/* set state to IDLE */
    847 		schizo_pbm_writeintr(pbm, clroff, 0);
    848  	}
    849 
    850 	return (ih);
    851 }
    852 
    853 static void *
    854 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
    855 	int (*func)(void *), void *arg)
    856 {
    857 	void *cookie;
    858 	struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie;
    859 
    860 	DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level));
    861 	cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg);
    862 
    863 	DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie));
    864 	return (cookie);
    865 }
    866