qvaux.c revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: qvaux.c,v 1.1.2.2 2015/09/22 12:05:53 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2015 The NetBSD Foundation, Inc. 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * This code is derived from software contributed to The NetBSD Foundation 8 1.1.2.2 skrll * by Charles H. Dickman 9 1.1.2.2 skrll * 10 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 skrll * modification, are permitted provided that the following conditions 12 1.1.2.2 skrll * are met: 13 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 18 1.1.2.2 skrll * 19 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 30 1.1.2.2 skrll */ 31 1.1.2.2 skrll 32 1.1.2.2 skrll /* 33 1.1.2.2 skrll * Copyright (c) 1992, 1993 34 1.1.2.2 skrll * The Regents of the University of California. All rights reserved. 35 1.1.2.2 skrll * 36 1.1.2.2 skrll * This code is derived from software contributed to Berkeley by 37 1.1.2.2 skrll * Ralph Campbell and Rick Macklem. 38 1.1.2.2 skrll * 39 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 40 1.1.2.2 skrll * modification, are permitted provided that the following conditions 41 1.1.2.2 skrll * are met: 42 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 43 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 44 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 45 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 46 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 47 1.1.2.2 skrll * 3. Neither the name of the University nor the names of its contributors 48 1.1.2.2 skrll * may be used to endorse or promote products derived from this software 49 1.1.2.2 skrll * without specific prior written permission. 50 1.1.2.2 skrll * 51 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 52 1.1.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 1.1.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 1.1.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 55 1.1.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 1.1.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 1.1.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 1.1.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 1.1.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 1.1.2.2 skrll * SUCH DAMAGE. 62 1.1.2.2 skrll */ 63 1.1.2.2 skrll 64 1.1.2.2 skrll /* 65 1.1.2.2 skrll * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 66 1.1.2.2 skrll * 67 1.1.2.2 skrll * This code is derived from software contributed to Berkeley by 68 1.1.2.2 skrll * Ralph Campbell and Rick Macklem. 69 1.1.2.2 skrll * 70 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 71 1.1.2.2 skrll * modification, are permitted provided that the following conditions 72 1.1.2.2 skrll * are met: 73 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 74 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 75 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 76 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 77 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 78 1.1.2.2 skrll * 3. All advertising materials mentioning features or use of this software 79 1.1.2.2 skrll * must display the following acknowledgement: 80 1.1.2.2 skrll * This product includes software developed by the University of 81 1.1.2.2 skrll * California, Berkeley and its contributors. 82 1.1.2.2 skrll * 4. Neither the name of the University nor the names of its contributors 83 1.1.2.2 skrll * may be used to endorse or promote products derived from this software 84 1.1.2.2 skrll * without specific prior written permission. 85 1.1.2.2 skrll * 86 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 87 1.1.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 88 1.1.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 89 1.1.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 90 1.1.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 91 1.1.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 92 1.1.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 93 1.1.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 94 1.1.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 95 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 96 1.1.2.2 skrll * SUCH DAMAGE. 97 1.1.2.2 skrll */ 98 1.1.2.2 skrll 99 1.1.2.2 skrll #include <sys/cdefs.h> 100 1.1.2.2 skrll __KERNEL_RCSID(0, "$$"); 101 1.1.2.2 skrll 102 1.1.2.2 skrll #include <sys/param.h> 103 1.1.2.2 skrll #include <sys/systm.h> 104 1.1.2.2 skrll #include <sys/callout.h> 105 1.1.2.2 skrll #include <sys/ioctl.h> 106 1.1.2.2 skrll #include <sys/tty.h> 107 1.1.2.2 skrll #include <sys/proc.h> 108 1.1.2.2 skrll #include <sys/buf.h> 109 1.1.2.2 skrll #include <sys/conf.h> 110 1.1.2.2 skrll #include <sys/file.h> 111 1.1.2.2 skrll #include <sys/uio.h> 112 1.1.2.2 skrll #include <sys/kernel.h> 113 1.1.2.2 skrll #include <sys/syslog.h> 114 1.1.2.2 skrll #include <sys/device.h> 115 1.1.2.2 skrll #include <sys/kauth.h> 116 1.1.2.2 skrll 117 1.1.2.2 skrll #include <sys/bus.h> 118 1.1.2.2 skrll #include <dev/qbus/ubavar.h> 119 1.1.2.2 skrll 120 1.1.2.2 skrll #include <vax/uba/qvareg.h> 121 1.1.2.2 skrll #include <vax/uba/qvavar.h> 122 1.1.2.2 skrll #include <vax/uba/qvkbdvar.h> 123 1.1.2.2 skrll 124 1.1.2.2 skrll #include <dev/cons.h> 125 1.1.2.2 skrll #include "qv.h" 126 1.1.2.2 skrll #include "qvkbd.h" 127 1.1.2.2 skrll #include "qvms.h" 128 1.1.2.2 skrll #include "qv_ic.h" 129 1.1.2.2 skrll 130 1.1.2.2 skrll #define QVAUX_DELAY(x) /* nothing */ 131 1.1.2.2 skrll #define control inline 132 1.1.2.2 skrll 133 1.1.2.2 skrll static control uint 134 1.1.2.2 skrll qvaux_read1(struct qvaux_softc *sc, u_int off) 135 1.1.2.2 skrll { 136 1.1.2.2 skrll u_int rv; 137 1.1.2.2 skrll 138 1.1.2.2 skrll rv = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off); 139 1.1.2.2 skrll QVAUX_DELAY(1); 140 1.1.2.2 skrll return rv; 141 1.1.2.2 skrll } 142 1.1.2.2 skrll 143 1.1.2.2 skrll static control u_int 144 1.1.2.2 skrll qvaux_read2(struct qvaux_softc *sc, u_int off) 145 1.1.2.2 skrll { 146 1.1.2.2 skrll u_int rv; 147 1.1.2.2 skrll 148 1.1.2.2 skrll rv = bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 149 1.1.2.2 skrll QVAUX_DELAY(1); 150 1.1.2.2 skrll return rv; 151 1.1.2.2 skrll } 152 1.1.2.2 skrll 153 1.1.2.2 skrll static control void 154 1.1.2.2 skrll qvaux_write1(struct qvaux_softc *sc, u_int off, u_int val) 155 1.1.2.2 skrll { 156 1.1.2.2 skrll 157 1.1.2.2 skrll bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val); 158 1.1.2.2 skrll bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_qr.qr_firstreg, 159 1.1.2.2 skrll sc->sc_qr.qr_winsize, BUS_SPACE_BARRIER_WRITE | 160 1.1.2.2 skrll BUS_SPACE_BARRIER_READ); 161 1.1.2.2 skrll QVAUX_DELAY(10); 162 1.1.2.2 skrll } 163 1.1.2.2 skrll 164 1.1.2.2 skrll static control void 165 1.1.2.2 skrll qvaux_write2(struct qvaux_softc *sc, u_int off, u_int val) 166 1.1.2.2 skrll { 167 1.1.2.2 skrll 168 1.1.2.2 skrll bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val); 169 1.1.2.2 skrll bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_qr.qr_firstreg, 170 1.1.2.2 skrll sc->sc_qr.qr_winsize, BUS_SPACE_BARRIER_WRITE | 171 1.1.2.2 skrll BUS_SPACE_BARRIER_READ); 172 1.1.2.2 skrll QVAUX_DELAY(10); 173 1.1.2.2 skrll } 174 1.1.2.2 skrll 175 1.1.2.2 skrll #include "ioconf.h" 176 1.1.2.2 skrll 177 1.1.2.2 skrll /* Flags used to monitor modem bits, make them understood outside driver */ 178 1.1.2.2 skrll 179 1.1.2.2 skrll #define DML_DTR TIOCM_DTR 180 1.1.2.2 skrll #define DML_DCD TIOCM_CD 181 1.1.2.2 skrll #define DML_RI TIOCM_RI 182 1.1.2.2 skrll #define DML_BRK 0100000 /* no equivalent, we will mask */ 183 1.1.2.2 skrll 184 1.1.2.2 skrll static const struct speedtab qvauxspeedtab[] = 185 1.1.2.2 skrll { 186 1.1.2.2 skrll { 0, 0 }, 187 1.1.2.2 skrll { 75, CSR_B75 }, 188 1.1.2.2 skrll { 110, CSR_B110 }, 189 1.1.2.2 skrll { 134, CSR_B134 }, 190 1.1.2.2 skrll { 150, CSR_B150 }, 191 1.1.2.2 skrll { 300, CSR_B300 }, 192 1.1.2.2 skrll { 600, CSR_B600 }, 193 1.1.2.2 skrll { 1200, CSR_B1200 }, 194 1.1.2.2 skrll { 2000, CSR_B2000 }, 195 1.1.2.2 skrll { 2400, CSR_B2400 }, 196 1.1.2.2 skrll { 4800, CSR_B4800 }, 197 1.1.2.2 skrll { 7200, CSR_B7200 }, 198 1.1.2.2 skrll { 9600, CSR_B9600 }, 199 1.1.2.2 skrll { 19200, CSR_B19200 }, 200 1.1.2.2 skrll { -1, -1 } 201 1.1.2.2 skrll }; 202 1.1.2.2 skrll 203 1.1.2.2 skrll int qvaux_match(device_t, cfdata_t, void *); 204 1.1.2.2 skrll static void qvaux_attach(device_t , device_t , void *); 205 1.1.2.2 skrll static void qvauxstart(struct tty *); 206 1.1.2.2 skrll static int qvauxparam(struct tty *, struct termios *); 207 1.1.2.2 skrll static unsigned qvauxmctl(struct qvaux_softc *, int, int, int); 208 1.1.2.2 skrll //static void qvauxscan(void *); 209 1.1.2.2 skrll int qvauxgetc(struct qvaux_linestate *); 210 1.1.2.2 skrll void qvauxputc(struct qvaux_linestate *, int); 211 1.1.2.2 skrll 212 1.1.2.2 skrll static dev_type_open(qvauxopen); 213 1.1.2.2 skrll static dev_type_close(qvauxclose); 214 1.1.2.2 skrll static dev_type_read(qvauxread); 215 1.1.2.2 skrll static dev_type_write(qvauxwrite); 216 1.1.2.2 skrll static dev_type_ioctl(qvauxioctl); 217 1.1.2.2 skrll static dev_type_stop(qvauxstop); 218 1.1.2.2 skrll static dev_type_tty(qvauxtty); 219 1.1.2.2 skrll static dev_type_poll(qvauxpoll); 220 1.1.2.2 skrll 221 1.1.2.2 skrll const struct cdevsw qvaux_cdevsw = { 222 1.1.2.2 skrll qvauxopen, qvauxclose, qvauxread, qvauxwrite, qvauxioctl, 223 1.1.2.2 skrll qvauxstop, qvauxtty, qvauxpoll, nommap, ttykqfilter, nodiscard, D_TTY 224 1.1.2.2 skrll }; 225 1.1.2.2 skrll 226 1.1.2.2 skrll int qvaux_timer; /* true if timer started */ 227 1.1.2.2 skrll struct callout qvauxscan_ch; 228 1.1.2.2 skrll static struct cnm_state qvaux_cnm_state; 229 1.1.2.2 skrll 230 1.1.2.2 skrll CFATTACH_DECL_NEW(qvaux, sizeof(struct qvaux_softc), 231 1.1.2.2 skrll qvaux_match, qvaux_attach, NULL, NULL); 232 1.1.2.2 skrll 233 1.1.2.2 skrll #if NQVKBD > 0 || NQVMS > 0 234 1.1.2.2 skrll static int 235 1.1.2.2 skrll qvaux_print(void *aux, const char *name) 236 1.1.2.2 skrll { 237 1.1.2.2 skrll struct qvauxkm_attach_args *daa = aux; 238 1.1.2.2 skrll if (name == NULL) { 239 1.1.2.2 skrll aprint_normal(" line %d", daa->daa_line); 240 1.1.2.2 skrll } 241 1.1.2.2 skrll 242 1.1.2.2 skrll return QUIET; 243 1.1.2.2 skrll } 244 1.1.2.2 skrll #endif 245 1.1.2.2 skrll 246 1.1.2.2 skrll int 247 1.1.2.2 skrll qvaux_match(device_t parent, cfdata_t match, void *aux) 248 1.1.2.2 skrll { 249 1.1.2.2 skrll /* always match since we are physically part of parent */ 250 1.1.2.2 skrll return 1; 251 1.1.2.2 skrll } 252 1.1.2.2 skrll 253 1.1.2.2 skrll /*ARGSUSED*/ 254 1.1.2.2 skrll static void 255 1.1.2.2 skrll qvaux_attach(device_t parent, device_t self, void *aux) 256 1.1.2.2 skrll { 257 1.1.2.2 skrll struct qvaux_softc *sc = device_private(self); 258 1.1.2.2 skrll struct uba_attach_args *ua = aux; 259 1.1.2.2 skrll #if NQVKBD > 0 || NQVMS > 0 260 1.1.2.2 skrll struct qvauxkm_attach_args daa; 261 1.1.2.2 skrll #endif 262 1.1.2.2 skrll 263 1.1.2.2 skrll /* set floating DUART vector and enable interrupts */ 264 1.1.2.2 skrll qv_ic_setvec(ua, QVA_QVIC, QV_DUART_VEC, ua->ua_cvec); 265 1.1.2.2 skrll qv_ic_arm(ua, QVA_QVIC, QV_IC_ENA); 266 1.1.2.2 skrll bus_space_write_2(ua->ua_iot, ua->ua_ioh, QVA_QVCSR, 267 1.1.2.2 skrll bus_space_read_2(ua->ua_iot, ua->ua_ioh, QVA_QVCSR) | (1 << 6)); 268 1.1.2.2 skrll 269 1.1.2.2 skrll sc->sc_dev = self; 270 1.1.2.2 skrll sc->sc_iot = ua->ua_iot; 271 1.1.2.2 skrll sc->sc_ioh = ua->ua_ioh; 272 1.1.2.2 skrll 273 1.1.2.2 skrll /* device register access structure */ 274 1.1.2.2 skrll sc->sc_qr.qr_ipcr = DU_IPCR; 275 1.1.2.2 skrll sc->sc_qr.qr_acr = DU_ACR; 276 1.1.2.2 skrll sc->sc_qr.qr_isr = DU_ISR; 277 1.1.2.2 skrll sc->sc_qr. qr_imr = DU_IMR; 278 1.1.2.2 skrll sc->sc_qr.qr_ctur = DU_CTUR; 279 1.1.2.2 skrll sc->sc_qr.qr_ctlr = DU_CTLR; 280 1.1.2.2 skrll sc->sc_qr.qr_ip = DU_IP; 281 1.1.2.2 skrll sc->sc_qr.qr_opcr = DU_OPCR; 282 1.1.2.2 skrll sc->sc_qr.qr_cstrt = DU_IMR; 283 1.1.2.2 skrll sc->sc_qr.qr_opset = DU_OPSET; 284 1.1.2.2 skrll sc->sc_qr.qr_cstop = DU_CSTOP; 285 1.1.2.2 skrll sc->sc_qr.qr_opclr = DU_OPCLR; 286 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[0].qr_mr = CH_MR(0); 287 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[0].qr_sr = CH_SR(0); 288 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[0].qr_csr = CH_CSR(0); 289 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[0].qr_cr = CH_CR(0); 290 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[0].qr_dat = CH_DAT(0); 291 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[1].qr_mr = CH_MR(1); 292 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[1].qr_sr = CH_SR(1); 293 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[1].qr_csr = CH_CSR(1); 294 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[1].qr_cr = CH_CR(1); 295 1.1.2.2 skrll sc->sc_qr.qr_ch_regs[1].qr_dat = CH_DAT(1); 296 1.1.2.2 skrll 297 1.1.2.2 skrll sc->sc_qr.qr_firstreg = QVA_FIRSTREG; 298 1.1.2.2 skrll sc->sc_qr.qr_winsize = QVA_WINSIZE; 299 1.1.2.2 skrll 300 1.1.2.2 skrll /* register DUART interrupt handler */ 301 1.1.2.2 skrll uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 302 1.1.2.2 skrll qvauxint, sc, &sc->sc_tintrcnt); 303 1.1.2.2 skrll qv_ic_enable(ua, QVA_QVIC, QV_DUART_VEC, QV_IC_ENA); 304 1.1.2.2 skrll 305 1.1.2.2 skrll qvauxattach(sc, ua->ua_evcnt, -1); 306 1.1.2.2 skrll 307 1.1.2.2 skrll #if NQVKBD > 0 308 1.1.2.2 skrll /* XXX set line parameters */ 309 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_csr, 310 1.1.2.2 skrll (CSR_B4800 << 4) | CSR_B4800); 311 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_cr, CR_CMD_MR1 | CR_ENA_RX); 312 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_mr, MR1_CS8 | MR1_PNONE); 313 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_mr, MR2_STOP1); 314 1.1.2.2 skrll 315 1.1.2.2 skrll daa.daa_line = 0; 316 1.1.2.2 skrll daa.daa_flags = 0; 317 1.1.2.2 skrll config_found(self, &daa, qvaux_print); 318 1.1.2.2 skrll #endif 319 1.1.2.2 skrll #if NQVMS > 0 320 1.1.2.2 skrll /* XXX set line parameters */ 321 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_csr, 322 1.1.2.2 skrll (CSR_B4800 << 4) | CSR_B4800); 323 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_cr, CR_CMD_MR1 | CR_ENA_RX); 324 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_mr, MR1_CS8 | MR1_PODD); 325 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_mr, MR2_STOP1); 326 1.1.2.2 skrll 327 1.1.2.2 skrll daa.daa_line = 1; 328 1.1.2.2 skrll daa.daa_flags = 0; 329 1.1.2.2 skrll config_found(self, &daa, qvaux_print); 330 1.1.2.2 skrll #endif 331 1.1.2.2 skrll 332 1.1.2.2 skrll } 333 1.1.2.2 skrll 334 1.1.2.2 skrll void 335 1.1.2.2 skrll qvauxattach(struct qvaux_softc *sc, struct evcnt *parent_evcnt, int consline) 336 1.1.2.2 skrll { 337 1.1.2.2 skrll int n; 338 1.1.2.2 skrll dev_t dev; 339 1.1.2.2 skrll 340 1.1.2.2 skrll /* Initialize our softc structure. */ 341 1.1.2.2 skrll for (n = 0; n < NQVAUXLINE; n++) { 342 1.1.2.2 skrll sc->sc_qvaux[n].qvaux_sc = sc; 343 1.1.2.2 skrll sc->sc_qvaux[n].qvaux_line = n; 344 1.1.2.2 skrll sc->sc_qvaux[n].qvaux_tty = tty_alloc(); 345 1.1.2.2 skrll dev = sc->sc_qvaux[n].qvaux_tty->t_dev; 346 1.1.2.2 skrll sc->sc_qvaux[n].qvaux_tty->t_dev = makedev(major(dev),n); 347 1.1.2.2 skrll } 348 1.1.2.2 skrll 349 1.1.2.2 skrll evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, parent_evcnt, 350 1.1.2.2 skrll device_xname(sc->sc_dev), "rintr"); 351 1.1.2.2 skrll evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, parent_evcnt, 352 1.1.2.2 skrll device_xname(sc->sc_dev), "tintr"); 353 1.1.2.2 skrll 354 1.1.2.2 skrll /* Console magic keys */ 355 1.1.2.2 skrll cn_init_magic(&qvaux_cnm_state); 356 1.1.2.2 skrll cn_set_magic("\047\001"); /* default magic is BREAK */ 357 1.1.2.2 skrll /* VAX will change it in MD code */ 358 1.1.2.2 skrll 359 1.1.2.2 skrll sc->sc_rxint = sc->sc_brk = 0; 360 1.1.2.2 skrll sc->sc_consline = consline; 361 1.1.2.2 skrll 362 1.1.2.2 skrll sc->sc_imr = INT_RXA | INT_RXB; 363 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr); 364 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_cr, CR_ENA_TX | CR_ENA_RX); 365 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_cr, CR_ENA_TX | CR_ENA_RX); 366 1.1.2.2 skrll 367 1.1.2.2 skrll DELAY(10000); 368 1.1.2.2 skrll 369 1.1.2.2 skrll printf("\n"); 370 1.1.2.2 skrll } 371 1.1.2.2 skrll 372 1.1.2.2 skrll /* DUART Interrupt entry */ 373 1.1.2.2 skrll 374 1.1.2.2 skrll void 375 1.1.2.2 skrll qvauxint(void *arg) 376 1.1.2.2 skrll { 377 1.1.2.2 skrll struct qvaux_softc *sc = arg; 378 1.1.2.2 skrll int isr; 379 1.1.2.2 skrll 380 1.1.2.2 skrll isr = qvaux_read2(sc, sc->sc_qr.qr_isr); 381 1.1.2.2 skrll 382 1.1.2.2 skrll if (isr & (INT_RXA | INT_RXB | INT_BRKA | INT_BRKB)) 383 1.1.2.2 skrll qvauxrint(arg); 384 1.1.2.2 skrll 385 1.1.2.2 skrll isr = qvaux_read2(sc, sc->sc_qr.qr_isr); 386 1.1.2.2 skrll 387 1.1.2.2 skrll if (isr & (INT_TXA | INT_TXB) & sc->sc_imr) 388 1.1.2.2 skrll qvauxxint(arg); 389 1.1.2.2 skrll } 390 1.1.2.2 skrll 391 1.1.2.2 skrll /* Receiver Interrupt */ 392 1.1.2.2 skrll 393 1.1.2.2 skrll void 394 1.1.2.2 skrll qvauxrint(void *arg) 395 1.1.2.2 skrll { 396 1.1.2.2 skrll struct qvaux_softc *sc = arg; 397 1.1.2.2 skrll struct tty *tp; 398 1.1.2.2 skrll int cc, mcc, line; 399 1.1.2.2 skrll unsigned stat[2]; 400 1.1.2.2 skrll int overrun = 0; 401 1.1.2.2 skrll 402 1.1.2.2 skrll //printf(" qvauxrint "); 403 1.1.2.2 skrll 404 1.1.2.2 skrll sc->sc_rxint++; 405 1.1.2.2 skrll 406 1.1.2.2 skrll // determine source and loop until all are no longer active 407 1.1.2.2 skrll for (;;) { 408 1.1.2.2 skrll stat[0] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[0].qr_sr); 409 1.1.2.2 skrll stat[1] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[1].qr_sr); 410 1.1.2.2 skrll if ((stat[0] & SR_RX_RDY) == 0) { 411 1.1.2.2 skrll if ((stat[1] & SR_RX_RDY) == 0) 412 1.1.2.2 skrll break; 413 1.1.2.2 skrll else 414 1.1.2.2 skrll line = 1; 415 1.1.2.2 skrll } 416 1.1.2.2 skrll else 417 1.1.2.2 skrll line = 0; 418 1.1.2.2 skrll cc = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[line].qr_dat) & 0xFF; 419 1.1.2.2 skrll tp = sc->sc_qvaux[line].qvaux_tty; 420 1.1.2.2 skrll 421 1.1.2.2 skrll /* Must be caught early */ 422 1.1.2.2 skrll if (sc->sc_qvaux[line].qvaux_catch && 423 1.1.2.2 skrll (*sc->sc_qvaux[line].qvaux_catch)(sc->sc_qvaux[line] 424 1.1.2.2 skrll .qvaux_private, cc)) { 425 1.1.2.2 skrll continue; 426 1.1.2.2 skrll } 427 1.1.2.2 skrll 428 1.1.2.2 skrll if (stat[line] & SR_BREAK) // do SR error bits need to be 429 1.1.2.2 skrll // cleared by an error reset? 430 1.1.2.2 skrll mcc = CNC_BREAK; 431 1.1.2.2 skrll else 432 1.1.2.2 skrll mcc = cc; 433 1.1.2.2 skrll 434 1.1.2.2 skrll cn_check_magic(tp->t_dev, mcc, qvaux_cnm_state); 435 1.1.2.2 skrll 436 1.1.2.2 skrll if (!(tp->t_state & TS_ISOPEN)) { 437 1.1.2.2 skrll cv_broadcast(&tp->t_rawcv); 438 1.1.2.2 skrll continue; 439 1.1.2.2 skrll } 440 1.1.2.2 skrll 441 1.1.2.2 skrll if ((stat[line] & SR_OVERRUN) && overrun == 0) { // ? 442 1.1.2.2 skrll log(LOG_WARNING, "%s: silo overflow, line %d\n", 443 1.1.2.2 skrll device_xname(sc->sc_dev), line); 444 1.1.2.2 skrll overrun = 1; 445 1.1.2.2 skrll } 446 1.1.2.2 skrll 447 1.1.2.2 skrll if (stat[line] & SR_FRAME) // ? 448 1.1.2.2 skrll cc |= TTY_FE; 449 1.1.2.2 skrll if (stat[line] & SR_PARITY) // ? 450 1.1.2.2 skrll cc |= TTY_PE; 451 1.1.2.2 skrll 452 1.1.2.2 skrll (*tp->t_linesw->l_rint)(cc, tp); 453 1.1.2.2 skrll } 454 1.1.2.2 skrll } 455 1.1.2.2 skrll 456 1.1.2.2 skrll /* Transmitter Interrupt */ 457 1.1.2.2 skrll 458 1.1.2.2 skrll void 459 1.1.2.2 skrll qvauxxint(void *arg) 460 1.1.2.2 skrll { 461 1.1.2.2 skrll struct qvaux_softc *sc = arg; 462 1.1.2.2 skrll struct tty *tp; 463 1.1.2.2 skrll struct clist *cl; 464 1.1.2.2 skrll int line, ch, stat[2]; 465 1.1.2.2 skrll 466 1.1.2.2 skrll for (;;) { 467 1.1.2.2 skrll stat[0] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[0].qr_sr); 468 1.1.2.2 skrll stat[1] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[1].qr_sr); 469 1.1.2.2 skrll if (((stat[0] & SR_TX_RDY) == 0) 470 1.1.2.2 skrll || ((sc->sc_imr & INT_TXA) == 0)) { 471 1.1.2.2 skrll if (((stat[1] & SR_TX_RDY) == 0) 472 1.1.2.2 skrll || ((sc->sc_imr & INT_TXB) == 0)) 473 1.1.2.2 skrll break; 474 1.1.2.2 skrll else 475 1.1.2.2 skrll line = 1; 476 1.1.2.2 skrll } 477 1.1.2.2 skrll else 478 1.1.2.2 skrll line = 0; 479 1.1.2.2 skrll tp = sc->sc_qvaux[line].qvaux_tty; 480 1.1.2.2 skrll cl = &tp->t_outq; 481 1.1.2.2 skrll tp->t_state &= ~TS_BUSY; 482 1.1.2.2 skrll 483 1.1.2.2 skrll /* Just send out a char if we have one */ 484 1.1.2.2 skrll /* As long as we can fill the chip buffer, we just loop here */ 485 1.1.2.2 skrll // no fifo, just holding register 486 1.1.2.2 skrll if (cl->c_cc) { 487 1.1.2.2 skrll tp->t_state |= TS_BUSY; 488 1.1.2.2 skrll ch = getc(cl); 489 1.1.2.2 skrll qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_dat, ch); 490 1.1.2.2 skrll continue; 491 1.1.2.2 skrll } 492 1.1.2.2 skrll /* Nothing to send, clear the tx flags */ 493 1.1.2.2 skrll sc->sc_imr &= ~((line) ? (INT_TXB) : (INT_TXA)); 494 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr); 495 1.1.2.2 skrll 496 1.1.2.2 skrll if (sc->sc_qvaux[line].qvaux_catch) 497 1.1.2.2 skrll continue; 498 1.1.2.2 skrll 499 1.1.2.2 skrll if (tp->t_state & TS_FLUSH) 500 1.1.2.2 skrll tp->t_state &= ~TS_FLUSH; 501 1.1.2.2 skrll else 502 1.1.2.2 skrll ndflush (&tp->t_outq, cl->c_cc); 503 1.1.2.2 skrll 504 1.1.2.2 skrll (*tp->t_linesw->l_start)(tp); 505 1.1.2.2 skrll } 506 1.1.2.2 skrll } 507 1.1.2.2 skrll 508 1.1.2.2 skrll int 509 1.1.2.2 skrll qvauxopen(dev_t dev, int flag, int mode, struct lwp *l) 510 1.1.2.2 skrll { 511 1.1.2.2 skrll const int line = QVA_PORT(minor(dev)); 512 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 513 1.1.2.2 skrll QVA_I2C(minor(dev))); // only one controller 514 1.1.2.2 skrll struct tty *tp; 515 1.1.2.2 skrll int error = 0; 516 1.1.2.2 skrll 517 1.1.2.2 skrll if (sc == NULL || line >= NQVAUXLINE) 518 1.1.2.2 skrll return ENXIO; 519 1.1.2.2 skrll 520 1.1.2.2 skrll /* if some other device is using the line, it's busy */ 521 1.1.2.2 skrll if (sc->sc_qvaux[line].qvaux_catch) 522 1.1.2.2 skrll return EBUSY; 523 1.1.2.2 skrll 524 1.1.2.2 skrll tp = sc->sc_qvaux[line].qvaux_tty; 525 1.1.2.2 skrll if (tp == NULL) 526 1.1.2.2 skrll return (ENODEV); 527 1.1.2.2 skrll 528 1.1.2.2 skrll tp->t_oproc = qvauxstart; 529 1.1.2.2 skrll tp->t_param = qvauxparam; 530 1.1.2.2 skrll tp->t_dev = dev; 531 1.1.2.2 skrll 532 1.1.2.2 skrll if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 533 1.1.2.2 skrll return (EBUSY); 534 1.1.2.2 skrll 535 1.1.2.2 skrll if ((tp->t_state & TS_ISOPEN) == 0) { 536 1.1.2.2 skrll ttychars(tp); 537 1.1.2.2 skrll if (tp->t_ispeed == 0) { 538 1.1.2.2 skrll tp->t_iflag = TTYDEF_IFLAG; 539 1.1.2.2 skrll tp->t_oflag = TTYDEF_OFLAG; 540 1.1.2.2 skrll tp->t_cflag = TTYDEF_CFLAG; 541 1.1.2.2 skrll tp->t_lflag = TTYDEF_LFLAG; 542 1.1.2.2 skrll tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 543 1.1.2.2 skrll } 544 1.1.2.2 skrll (void) qvauxparam(tp, &tp->t_termios); 545 1.1.2.2 skrll ttsetwater(tp); 546 1.1.2.2 skrll } 547 1.1.2.2 skrll 548 1.1.2.2 skrll /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 549 1.1.2.2 skrll if (qvauxmctl(sc, line, DML_DTR, DMBIS) & DML_DCD) 550 1.1.2.2 skrll tp->t_state |= TS_CARR_ON; 551 1.1.2.2 skrll mutex_spin_enter(&tty_lock); 552 1.1.2.2 skrll while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 553 1.1.2.2 skrll !(tp->t_state & TS_CARR_ON)) { 554 1.1.2.2 skrll tp->t_wopen++; 555 1.1.2.2 skrll error = ttysleep(tp, &tp->t_rawcv, true, 0); 556 1.1.2.2 skrll tp->t_wopen--; 557 1.1.2.2 skrll if (error) 558 1.1.2.2 skrll break; 559 1.1.2.2 skrll } 560 1.1.2.2 skrll mutex_spin_exit(&tty_lock); 561 1.1.2.2 skrll if (error) 562 1.1.2.2 skrll return (error); 563 1.1.2.2 skrll return ((*tp->t_linesw->l_open)(dev, tp)); 564 1.1.2.2 skrll } 565 1.1.2.2 skrll 566 1.1.2.2 skrll /*ARGSUSED*/ 567 1.1.2.2 skrll int 568 1.1.2.2 skrll qvauxclose(dev_t dev, int flag, int mode, struct lwp *l) 569 1.1.2.2 skrll { 570 1.1.2.2 skrll const int line = QVA_PORT(minor(dev)); 571 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 572 1.1.2.2 skrll QVA_I2C(minor(dev))); // only one controller 573 1.1.2.2 skrll struct tty *tp = sc->sc_qvaux[line].qvaux_tty; 574 1.1.2.2 skrll 575 1.1.2.2 skrll (*tp->t_linesw->l_close)(tp, flag); 576 1.1.2.2 skrll 577 1.1.2.2 skrll /* Make sure a BREAK state is not left enabled. */ 578 1.1.2.2 skrll (void) qvauxmctl(sc, line, DML_BRK, DMBIC); 579 1.1.2.2 skrll 580 1.1.2.2 skrll /* Do a hangup if so required. */ 581 1.1.2.2 skrll if ((tp->t_cflag & HUPCL) || tp->t_wopen || !(tp->t_state & TS_ISOPEN)) 582 1.1.2.2 skrll (void) qvauxmctl(sc, line, 0, DMSET); 583 1.1.2.2 skrll 584 1.1.2.2 skrll return ttyclose(tp); 585 1.1.2.2 skrll } 586 1.1.2.2 skrll 587 1.1.2.2 skrll int 588 1.1.2.2 skrll qvauxread(dev_t dev, struct uio *uio, int flag) 589 1.1.2.2 skrll { 590 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 591 1.1.2.2 skrll QVA_I2C(minor(dev))); // only one controller 592 1.1.2.2 skrll struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty; 593 1.1.2.2 skrll 594 1.1.2.2 skrll return ((*tp->t_linesw->l_read)(tp, uio, flag)); 595 1.1.2.2 skrll } 596 1.1.2.2 skrll 597 1.1.2.2 skrll int 598 1.1.2.2 skrll qvauxwrite(dev_t dev, struct uio *uio, int flag) 599 1.1.2.2 skrll { 600 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 601 1.1.2.2 skrll QVA_I2C(minor(dev))); // only one controller 602 1.1.2.2 skrll struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty; 603 1.1.2.2 skrll 604 1.1.2.2 skrll return ((*tp->t_linesw->l_write)(tp, uio, flag)); 605 1.1.2.2 skrll } 606 1.1.2.2 skrll 607 1.1.2.2 skrll int 608 1.1.2.2 skrll qvauxpoll(dev_t dev, int events, struct lwp *l) 609 1.1.2.2 skrll { 610 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 611 1.1.2.2 skrll QVA_I2C(minor(dev))); // only one controller 612 1.1.2.2 skrll struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty; 613 1.1.2.2 skrll 614 1.1.2.2 skrll return ((*tp->t_linesw->l_poll)(tp, events, l)); 615 1.1.2.2 skrll } 616 1.1.2.2 skrll 617 1.1.2.2 skrll /*ARGSUSED*/ 618 1.1.2.2 skrll int 619 1.1.2.2 skrll qvauxioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 620 1.1.2.2 skrll { 621 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 622 1.1.2.2 skrll QVA_I2C(minor(dev))); // only one controller 623 1.1.2.2 skrll const int line = QVA_PORT(minor(dev)); 624 1.1.2.2 skrll struct tty *tp = sc->sc_qvaux[line].qvaux_tty; 625 1.1.2.2 skrll int error; 626 1.1.2.2 skrll 627 1.1.2.2 skrll error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 628 1.1.2.2 skrll if (error >= 0) 629 1.1.2.2 skrll return (error); 630 1.1.2.2 skrll 631 1.1.2.2 skrll error = ttioctl(tp, cmd, data, flag, l); 632 1.1.2.2 skrll if (error >= 0) 633 1.1.2.2 skrll return (error); 634 1.1.2.2 skrll 635 1.1.2.2 skrll switch (cmd) { 636 1.1.2.2 skrll case TIOCSBRK: 637 1.1.2.2 skrll (void) qvauxmctl(sc, line, DML_BRK, DMBIS); 638 1.1.2.2 skrll break; 639 1.1.2.2 skrll 640 1.1.2.2 skrll case TIOCCBRK: 641 1.1.2.2 skrll (void) qvauxmctl(sc, line, DML_BRK, DMBIC); 642 1.1.2.2 skrll break; 643 1.1.2.2 skrll 644 1.1.2.2 skrll case TIOCSDTR: 645 1.1.2.2 skrll (void) qvauxmctl(sc, line, DML_DTR, DMBIS); 646 1.1.2.2 skrll break; 647 1.1.2.2 skrll 648 1.1.2.2 skrll case TIOCCDTR: 649 1.1.2.2 skrll (void) qvauxmctl(sc, line, DML_DTR, DMBIC); 650 1.1.2.2 skrll break; 651 1.1.2.2 skrll 652 1.1.2.2 skrll case TIOCMSET: 653 1.1.2.2 skrll (void) qvauxmctl(sc, line, *(int *)data, DMSET); 654 1.1.2.2 skrll break; 655 1.1.2.2 skrll 656 1.1.2.2 skrll case TIOCMBIS: 657 1.1.2.2 skrll (void) qvauxmctl(sc, line, *(int *)data, DMBIS); 658 1.1.2.2 skrll break; 659 1.1.2.2 skrll 660 1.1.2.2 skrll case TIOCMBIC: 661 1.1.2.2 skrll (void) qvauxmctl(sc, line, *(int *)data, DMBIC); 662 1.1.2.2 skrll break; 663 1.1.2.2 skrll 664 1.1.2.2 skrll case TIOCMGET: 665 1.1.2.2 skrll *(int *)data = (qvauxmctl(sc, line, 0, DMGET) & ~DML_BRK); 666 1.1.2.2 skrll break; 667 1.1.2.2 skrll 668 1.1.2.2 skrll default: 669 1.1.2.2 skrll return (EPASSTHROUGH); 670 1.1.2.2 skrll } 671 1.1.2.2 skrll return (0); 672 1.1.2.2 skrll } 673 1.1.2.2 skrll 674 1.1.2.2 skrll struct tty * 675 1.1.2.2 skrll qvauxtty(dev_t dev) 676 1.1.2.2 skrll { 677 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 678 1.1.2.2 skrll QVA_I2C(minor(dev))); 679 1.1.2.2 skrll 680 1.1.2.2 skrll return sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty; 681 1.1.2.2 skrll } 682 1.1.2.2 skrll 683 1.1.2.2 skrll /*ARGSUSED*/ 684 1.1.2.2 skrll void 685 1.1.2.2 skrll qvauxstop(struct tty *tp, int flag) 686 1.1.2.2 skrll { 687 1.1.2.2 skrll if ((tp->t_state & (TS_BUSY | TS_TTSTOP)) == TS_BUSY) 688 1.1.2.2 skrll tp->t_state |= TS_FLUSH; 689 1.1.2.2 skrll } 690 1.1.2.2 skrll 691 1.1.2.2 skrll void 692 1.1.2.2 skrll qvauxstart(struct tty *tp) 693 1.1.2.2 skrll { 694 1.1.2.2 skrll struct qvaux_softc *sc; 695 1.1.2.2 skrll int line; 696 1.1.2.2 skrll int s; 697 1.1.2.2 skrll 698 1.1.2.2 skrll s = spltty(); 699 1.1.2.2 skrll if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) { 700 1.1.2.2 skrll splx(s); 701 1.1.2.2 skrll return; 702 1.1.2.2 skrll } 703 1.1.2.2 skrll if (!ttypull(tp)) { 704 1.1.2.2 skrll splx(s); 705 1.1.2.2 skrll return; 706 1.1.2.2 skrll } 707 1.1.2.2 skrll 708 1.1.2.2 skrll line = QVA_PORT(minor(tp->t_dev)); 709 1.1.2.2 skrll sc = device_lookup_private(&qvaux_cd, QVA_I2C(minor(tp->t_dev))); 710 1.1.2.2 skrll 711 1.1.2.2 skrll tp->t_state |= TS_BUSY; 712 1.1.2.2 skrll sc->sc_imr |= ((line) ? (INT_TXB) : (INT_TXA)); 713 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr); 714 1.1.2.2 skrll qvauxxint(sc); 715 1.1.2.2 skrll splx(s); 716 1.1.2.2 skrll } 717 1.1.2.2 skrll 718 1.1.2.2 skrll static int 719 1.1.2.2 skrll qvauxparam(struct tty *tp, struct termios *t) 720 1.1.2.2 skrll { 721 1.1.2.2 skrll struct qvaux_softc *sc = device_lookup_private(&qvaux_cd, 722 1.1.2.2 skrll QVA_I2C(minor(tp->t_dev))); 723 1.1.2.2 skrll const int line = QVA_PORT(minor(tp->t_dev)); 724 1.1.2.2 skrll int cflag = t->c_cflag; 725 1.1.2.2 skrll int ispeed = ttspeedtab(t->c_ispeed, qvauxspeedtab); 726 1.1.2.2 skrll int ospeed = ttspeedtab(t->c_ospeed, qvauxspeedtab); 727 1.1.2.2 skrll unsigned mr1, mr2; 728 1.1.2.2 skrll int s; 729 1.1.2.2 skrll 730 1.1.2.2 skrll 731 1.1.2.2 skrll /* check requested parameters */ 732 1.1.2.2 skrll if (ospeed < 0 || ispeed < 0) 733 1.1.2.2 skrll return (EINVAL); 734 1.1.2.2 skrll 735 1.1.2.2 skrll tp->t_ispeed = t->c_ispeed; 736 1.1.2.2 skrll tp->t_ospeed = t->c_ospeed; 737 1.1.2.2 skrll tp->t_cflag = cflag; 738 1.1.2.2 skrll 739 1.1.2.2 skrll if (ospeed == 0) { 740 1.1.2.2 skrll (void) qvauxmctl(sc, line, 0, DMSET); /* hang up line */ 741 1.1.2.2 skrll return (0); 742 1.1.2.2 skrll } 743 1.1.2.2 skrll 744 1.1.2.2 skrll s = spltty(); 745 1.1.2.2 skrll 746 1.1.2.2 skrll /* XXX This is wrong. Flush output or the chip gets very confused. */ 747 1.1.2.2 skrll //ttywait(tp); 748 1.1.2.2 skrll 749 1.1.2.2 skrll //lpr = DZ_LPR_RX_ENABLE | ((ispeed&0xF)<<8) | line; 750 1.1.2.2 skrll 751 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_acr, ACR_BRG); 752 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_csr, 753 1.1.2.2 skrll (ispeed << 4) | ospeed); 754 1.1.2.2 skrll 755 1.1.2.2 skrll mr1 = mr2 = 0; 756 1.1.2.2 skrll 757 1.1.2.2 skrll switch (cflag & CSIZE) 758 1.1.2.2 skrll { 759 1.1.2.2 skrll case CS5: 760 1.1.2.2 skrll mr1 |= MR1_CS5; 761 1.1.2.2 skrll break; 762 1.1.2.2 skrll case CS6: 763 1.1.2.2 skrll mr1 |= MR1_CS6; 764 1.1.2.2 skrll break; 765 1.1.2.2 skrll case CS7: 766 1.1.2.2 skrll mr1 |= MR1_CS7; 767 1.1.2.2 skrll break; 768 1.1.2.2 skrll default: 769 1.1.2.2 skrll mr1 |= MR1_CS8; 770 1.1.2.2 skrll break; 771 1.1.2.2 skrll } 772 1.1.2.2 skrll if (cflag & PARENB) { 773 1.1.2.2 skrll if (cflag & PARODD) 774 1.1.2.2 skrll mr1 |= MR1_PODD; 775 1.1.2.2 skrll else 776 1.1.2.2 skrll mr1 |= MR1_PEVEN; 777 1.1.2.2 skrll } 778 1.1.2.2 skrll else 779 1.1.2.2 skrll mr1 |= MR1_PNONE; 780 1.1.2.2 skrll if (cflag & CSTOPB) 781 1.1.2.2 skrll mr2 |= MR2_STOP2; 782 1.1.2.2 skrll else 783 1.1.2.2 skrll mr2 |= MR2_STOP1; 784 1.1.2.2 skrll 785 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_cr, 786 1.1.2.2 skrll CR_CMD_MR1 | CR_ENA_RX); // reset to mr1 787 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_mr, mr1); 788 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_mr, mr2); 789 1.1.2.2 skrll qvaux_write2(sc, sc->sc_qr.qr_acr, ACR_BRG); 790 1.1.2.2 skrll (void) splx(s); 791 1.1.2.2 skrll DELAY(10000); 792 1.1.2.2 skrll 793 1.1.2.2 skrll return (0); 794 1.1.2.2 skrll } 795 1.1.2.2 skrll 796 1.1.2.2 skrll // QVSS has no modem control signals 797 1.1.2.2 skrll static unsigned 798 1.1.2.2 skrll qvauxmctl(struct qvaux_softc *sc, int line, int bits, int how) 799 1.1.2.2 skrll { 800 1.1.2.2 skrll /* unsigned status; */ 801 1.1.2.2 skrll unsigned mbits; 802 1.1.2.2 skrll unsigned bit; 803 1.1.2.2 skrll int s; 804 1.1.2.2 skrll 805 1.1.2.2 skrll s = spltty(); 806 1.1.2.2 skrll mbits = 0; 807 1.1.2.2 skrll bit = (1 << line); 808 1.1.2.2 skrll #if 0 809 1.1.2.2 skrll 810 1.1.2.2 skrll /* external signals as seen from the port */ 811 1.1.2.2 skrll status = qvaux_read1(sc, sc->sc_dr.dr_dcd) | sc->sc_dsr; 812 1.1.2.2 skrll if (status & bit) 813 1.1.2.2 skrll mbits |= DML_DCD; 814 1.1.2.2 skrll status = qvaux_read1(sc, sc->sc_dr.dr_ring); 815 1.1.2.2 skrll if (status & bit) 816 1.1.2.2 skrll mbits |= DML_RI; 817 1.1.2.2 skrll 818 1.1.2.2 skrll /* internal signals/state delivered to port */ 819 1.1.2.2 skrll status = qvaux_read1(sc, sc->sc_dr.dr_dtr); 820 1.1.2.2 skrll if (status & bit) 821 1.1.2.2 skrll mbits |= DML_DTR; 822 1.1.2.2 skrll #endif 823 1.1.2.2 skrll if (sc->sc_brk & bit) 824 1.1.2.2 skrll mbits |= DML_BRK; 825 1.1.2.2 skrll 826 1.1.2.2 skrll switch (how) 827 1.1.2.2 skrll { 828 1.1.2.2 skrll case DMSET: 829 1.1.2.2 skrll mbits = bits; 830 1.1.2.2 skrll break; 831 1.1.2.2 skrll 832 1.1.2.2 skrll case DMBIS: 833 1.1.2.2 skrll mbits |= bits; 834 1.1.2.2 skrll break; 835 1.1.2.2 skrll 836 1.1.2.2 skrll case DMBIC: 837 1.1.2.2 skrll mbits &= ~bits; 838 1.1.2.2 skrll break; 839 1.1.2.2 skrll 840 1.1.2.2 skrll case DMGET: 841 1.1.2.2 skrll (void) splx(s); 842 1.1.2.2 skrll return (mbits); 843 1.1.2.2 skrll } 844 1.1.2.2 skrll #if 0 845 1.1.2.2 skrll if (mbits & DML_DTR) { 846 1.1.2.2 skrll qvaux_write1(sc, sc->sc_dr.dr_dtr, 847 1.1.2.2 skrll qvaux_read1(sc, sc->sc_dr.dr_dtr) | bit); 848 1.1.2.2 skrll } else { 849 1.1.2.2 skrll qvaux_write1(sc, sc->sc_dr.dr_dtr, 850 1.1.2.2 skrll qvaux_read1(sc, sc->sc_dr.dr_dtr) & ~bit); 851 1.1.2.2 skrll } 852 1.1.2.2 skrll #endif 853 1.1.2.2 skrll if (mbits & DML_BRK) { 854 1.1.2.2 skrll sc->sc_brk |= bit; 855 1.1.2.2 skrll qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_cr, 856 1.1.2.2 skrll CR_CMD_START_BRK); 857 1.1.2.2 skrll } else { 858 1.1.2.2 skrll sc->sc_brk &= ~bit; 859 1.1.2.2 skrll qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_cr, 860 1.1.2.2 skrll CR_CMD_STOP_BRK); 861 1.1.2.2 skrll } 862 1.1.2.2 skrll 863 1.1.2.2 skrll (void) splx(s); 864 1.1.2.2 skrll 865 1.1.2.2 skrll return (mbits); 866 1.1.2.2 skrll } 867 1.1.2.2 skrll 868 1.1.2.2 skrll /* 869 1.1.2.2 skrll * Called after an ubareset. The QVSS card is reset, but the only thing 870 1.1.2.2 skrll * that must be done is to start the receiver and transmitter again. 871 1.1.2.2 skrll * No DMA setup to care about. 872 1.1.2.2 skrll */ 873 1.1.2.2 skrll void 874 1.1.2.2 skrll qvauxreset(device_t dev) 875 1.1.2.2 skrll { 876 1.1.2.2 skrll struct qvaux_softc *sc = device_private(dev); 877 1.1.2.2 skrll struct tty *tp; 878 1.1.2.2 skrll int i; 879 1.1.2.2 skrll 880 1.1.2.2 skrll for (i = 0; i < NQVAUXLINE; i++) { 881 1.1.2.2 skrll tp = sc->sc_qvaux[i].qvaux_tty; 882 1.1.2.2 skrll 883 1.1.2.2 skrll if (((tp->t_state & TS_ISOPEN) == 0) || (tp->t_wopen == 0)) 884 1.1.2.2 skrll continue; 885 1.1.2.2 skrll 886 1.1.2.2 skrll qvauxparam(tp, &tp->t_termios); 887 1.1.2.2 skrll qvauxmctl(sc, i, DML_DTR, DMSET); 888 1.1.2.2 skrll tp->t_state &= ~TS_BUSY; 889 1.1.2.2 skrll qvauxstart(tp); /* Kick off transmitter again */ 890 1.1.2.2 skrll } 891 1.1.2.2 skrll } 892 1.1.2.2 skrll 893 1.1.2.2 skrll #if NQVKBD > 0 || NQVMS > 0 894 1.1.2.2 skrll int 895 1.1.2.2 skrll qvauxgetc(struct qvaux_linestate *ls) 896 1.1.2.2 skrll { 897 1.1.2.2 skrll #if 0 898 1.1.2.2 skrll int line = ls->qvaux_line; 899 1.1.2.2 skrll int s; 900 1.1.2.2 skrll u_short rbuf; 901 1.1.2.2 skrll 902 1.1.2.2 skrll s = spltty(); 903 1.1.2.2 skrll for (;;) { 904 1.1.2.2 skrll for(; (dz->csr & DZ_CSR_RX_DONE) == 0;); 905 1.1.2.2 skrll rbuf = dz->rbuf; 906 1.1.2.2 skrll if (((rbuf >> 8) & 3) == line) { 907 1.1.2.2 skrll splx(s); 908 1.1.2.2 skrll return (rbuf & 0xff); 909 1.1.2.2 skrll } 910 1.1.2.2 skrll } 911 1.1.2.2 skrll #endif 912 1.1.2.2 skrll return 0; 913 1.1.2.2 skrll } 914 1.1.2.2 skrll 915 1.1.2.2 skrll void 916 1.1.2.2 skrll qvauxputc(struct qvaux_linestate *ls, int ch) 917 1.1.2.2 skrll { 918 1.1.2.2 skrll //int line; 919 1.1.2.2 skrll int s; 920 1.1.2.2 skrll 921 1.1.2.2 skrll /* if the qvaux has already been attached, the MI 922 1.1.2.2 skrll driver will do the transmitting: */ 923 1.1.2.2 skrll if (ls && ls->qvaux_sc) { 924 1.1.2.2 skrll s = spltty(); 925 1.1.2.2 skrll // line = ls->qvaux_line; 926 1.1.2.2 skrll putc(ch, &ls->qvaux_tty->t_outq); 927 1.1.2.2 skrll qvauxstart(ls->qvaux_tty); 928 1.1.2.2 skrll splx(s); 929 1.1.2.2 skrll return; 930 1.1.2.2 skrll } 931 1.1.2.2 skrll 932 1.1.2.2 skrll /* use qvauxcnputc to do the transmitting: */ 933 1.1.2.2 skrll //qvauxcnputc(makedev(cdevsw_lookup_major(&qvaux_cdevsw), 0), ch); 934 1.1.2.2 skrll } 935 1.1.2.2 skrll #endif /* NQVKBD > 0 || NQVMS > 0 */ 936
Indexes created Sat Nov 01 21:09:44 GMT 2025