11.26Spgoyette/* $NetBSD: spdmem_i2c.c,v 1.26 2022/03/30 00:06:50 pgoyette Exp $ */ 21.1Spgoyette 31.1Spgoyette/* 41.1Spgoyette * Copyright (c) 2007 Nicolas Joly 51.1Spgoyette * Copyright (c) 2007 Paul Goyette 61.1Spgoyette * Copyright (c) 2007 Tobias Nygren 71.11Smlelstv * Copyright (c) 2015 Michael van Elst 81.1Spgoyette * All rights reserved. 91.1Spgoyette * 101.1Spgoyette * Redistribution and use in source and binary forms, with or without 111.1Spgoyette * modification, are permitted provided that the following conditions 121.1Spgoyette * are met: 131.1Spgoyette * 1. Redistributions of source code must retain the above copyright 141.1Spgoyette * notice, this list of conditions and the following disclaimer. 151.1Spgoyette * 2. Redistributions in binary form must reproduce the above copyright 161.1Spgoyette * notice, this list of conditions and the following disclaimer in the 171.1Spgoyette * documentation and/or other materials provided with the distribution. 181.1Spgoyette * 3. The name of the author may not be used to endorse or promote products 191.1Spgoyette * derived from this software without specific prior written permission. 201.1Spgoyette * 211.1Spgoyette * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 221.1Spgoyette * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 231.1Spgoyette * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 241.1Spgoyette * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 251.1Spgoyette * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 261.1Spgoyette * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 271.1Spgoyette * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 281.1Spgoyette * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 291.1Spgoyette * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 301.1Spgoyette * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 311.1Spgoyette * POSSIBILITY OF SUCH DAMAGE. 321.1Spgoyette */ 331.1Spgoyette 341.1Spgoyette/* 351.1Spgoyette * Serial Presence Detect (SPD) memory identification 361.11Smlelstv * 371.11Smlelstv * JEDEC standard No. 21-C 381.11Smlelstv * JEDEC document 4_01_06R24 391.11Smlelstv * - Definitions of the EE1004-v 4 Kbit Serial Presence Detect EEPROM [...] 401.1Spgoyette */ 411.1Spgoyette 421.1Spgoyette#include <sys/cdefs.h> 431.26Spgoyette__KERNEL_RCSID(0, "$NetBSD: spdmem_i2c.c,v 1.26 2022/03/30 00:06:50 pgoyette Exp $"); 441.1Spgoyette 451.1Spgoyette#include <sys/param.h> 461.1Spgoyette#include <sys/device.h> 471.1Spgoyette#include <sys/endian.h> 481.2Spgoyette#include <sys/module.h> 491.1Spgoyette#include <sys/sysctl.h> 501.1Spgoyette#include <machine/bswap.h> 511.1Spgoyette 521.1Spgoyette#include <dev/i2c/i2cvar.h> 531.1Spgoyette#include <dev/ic/spdmemreg.h> 541.1Spgoyette#include <dev/ic/spdmemvar.h> 551.1Spgoyette 561.1Spgoyette/* Constants for matching i2c bus address */ 571.11Smlelstv#define SPDMEM_I2C_ADDRMASK 0xfff8 581.1Spgoyette#define SPDMEM_I2C_ADDR 0x50 591.11Smlelstv#define SPDCTL_I2C_ADDR 0x30 601.11Smlelstv 611.11Smlelstv/* set write protection */ 621.11Smlelstv#define SPDCTL_SWP0 (SPDCTL_I2C_ADDR + 1) 631.11Smlelstv#define SPDCTL_SWP1 (SPDCTL_I2C_ADDR + 4) 641.11Smlelstv#define SPDCTL_SWP2 (SPDCTL_I2C_ADDR + 5) 651.11Smlelstv#define SPDCTL_SWP3 (SPDCTL_I2C_ADDR + 0) 661.11Smlelstv 671.11Smlelstv/* clear write protections */ 681.11Smlelstv#define SPDCTL_CWP (SPDCTL_I2C_ADDR + 3) 691.11Smlelstv 701.11Smlelstv/* read protection status */ 711.11Smlelstv#define SPDCTL_RPS0 (SPDCTL_I2C_ADDR + 1) 721.11Smlelstv#define SPDCTL_RPS1 (SPDCTL_I2C_ADDR + 4) 731.11Smlelstv#define SPDCTL_RPS2 (SPDCTL_I2C_ADDR + 5) 741.11Smlelstv#define SPDCTL_RPS3 (SPDCTL_I2C_ADDR + 0) 751.11Smlelstv 761.11Smlelstv/* select page address */ 771.11Smlelstv#define SPDCTL_SPA0 (SPDCTL_I2C_ADDR + 6) 781.11Smlelstv#define SPDCTL_SPA1 (SPDCTL_I2C_ADDR + 7) 791.11Smlelstv 801.11Smlelstv/* read page address */ 811.11Smlelstv#define SPDCTL_RPA (SPDCTL_I2C_ADDR + 6) 821.1Spgoyette 831.1Spgoyettestruct spdmem_i2c_softc { 841.1Spgoyette struct spdmem_softc sc_base; 851.1Spgoyette i2c_tag_t sc_tag; 861.11Smlelstv i2c_addr_t sc_addr; /* EEPROM */ 871.11Smlelstv i2c_addr_t sc_page0; 881.11Smlelstv i2c_addr_t sc_page1; 891.1Spgoyette}; 901.1Spgoyette 911.13Smsaitohstatic int spdmem_reset_page(struct spdmem_i2c_softc *); 921.2Spgoyettestatic int spdmem_i2c_match(device_t, cfdata_t, void *); 931.1Spgoyettestatic void spdmem_i2c_attach(device_t, device_t, void *); 941.2Spgoyettestatic int spdmem_i2c_detach(device_t, int); 951.2Spgoyette 961.2SpgoyetteCFATTACH_DECL_NEW(spdmem_iic, sizeof(struct spdmem_i2c_softc), 971.2Spgoyette spdmem_i2c_match, spdmem_i2c_attach, spdmem_i2c_detach, NULL); 981.1Spgoyette 991.12Smsaitohstatic int spdmem_i2c_read(struct spdmem_softc *, uint16_t, uint8_t *); 1001.1Spgoyette 1011.1Spgoyettestatic int 1021.13Smsaitohspdmem_reset_page(struct spdmem_i2c_softc *sc) 1031.13Smsaitoh{ 1041.13Smsaitoh uint8_t reg, byte0, byte2; 1051.14Spgoyette static uint8_t dummy = 0; 1061.13Smsaitoh int rv; 1071.13Smsaitoh 1081.13Smsaitoh reg = 0; 1091.13Smsaitoh 1101.22Smlelstv rv = iic_acquire_bus(sc->sc_tag, 0); 1111.22Smlelstv if (rv) 1121.22Smlelstv return rv; 1131.13Smsaitoh 1141.13Smsaitoh /* 1151.13Smsaitoh * Try to read byte 0 and 2. If it failed, it's not spdmem or a device 1161.13Smsaitoh * doesn't exist at the address. 1171.13Smsaitoh */ 1181.13Smsaitoh rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, ®, 1, 1191.18Sthorpej &byte0, 1, 0); 1201.24Smsaitoh if (rv != 0) 1211.24Smsaitoh goto error; 1221.24Smsaitoh 1231.23Smsaitoh reg = 2; 1241.25Smsaitoh rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, ®, 1, 1251.18Sthorpej &byte2, 1, 0); 1261.13Smsaitoh if (rv != 0) 1271.13Smsaitoh goto error; 1281.13Smsaitoh 1291.13Smsaitoh /* 1301.13Smsaitoh * Quirk for BIOSes that leave page 1 of a 4kbit EEPROM selected. 1311.13Smsaitoh * 1321.13Smsaitoh * byte0 is the length, byte2 is the memory type. Both of them should 1331.13Smsaitoh * not be zero. If zero, the current page might be 1 (DDR4 and newer). 1341.13Smsaitoh * If page 1 is selected, offset 0 can be 0 (Module Characteristics 1351.13Smsaitoh * (Energy backup is not available)) and also offset 2 can be 0 1361.13Smsaitoh * (Megabytes, and a part of Capacity digits). 1371.13Smsaitoh * 1381.13Smsaitoh * Note: The encoding of byte0 is vary in memory type, so we check 1391.13Smsaitoh * just with zero to be simple. 1401.13Smsaitoh * 1411.13Smsaitoh * Try to see if we are not at page 0. If it's not, select page 0. 1421.13Smsaitoh */ 1431.13Smsaitoh if ((byte0 == 0) || (byte2 == 0)) { 1441.13Smsaitoh /* 1451.13Smsaitoh * Note that SDCTL_RPA is the same as sc->sc_page0(SPDCTL_SPA0) 1461.13Smsaitoh * Write is SPA0, read is RPA. 1471.13Smsaitoh * 1481.13Smsaitoh * This call returns 0 on page 0 and returns -1 on page 1. 1491.13Smsaitoh * I don't know whether our icc_exec()'s API is good or not. 1501.13Smsaitoh */ 1511.13Smsaitoh rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_page0, 1521.18Sthorpej ®, 1, &dummy, 1, 0); 1531.13Smsaitoh if (rv != 0) { 1541.13Smsaitoh /* 1551.13Smsaitoh * The possibilities are: 1561.13Smsaitoh * a) page 1 is selected. 1571.13Smsaitoh * b) The device doesn't support page select and 1581.13Smsaitoh * it's not a SPD ROM. 1591.13Smsaitoh * Is there no way to distinguish them now? 1601.13Smsaitoh */ 1611.13Smsaitoh rv = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 1621.18Sthorpej sc->sc_page0, ®, 1, &dummy, 1, 0); 1631.13Smsaitoh if (rv == 0) { 1641.13Smsaitoh aprint_debug("Page 1 was selected. Page 0 is " 1651.13Smsaitoh "selected now.\n"); 1661.13Smsaitoh } else { 1671.13Smsaitoh aprint_debug("Failed to select page 0. This " 1681.13Smsaitoh "device isn't SPD ROM\n"); 1691.13Smsaitoh } 1701.13Smsaitoh } else { 1711.13Smsaitoh /* This device isn't SPD ROM */ 1721.13Smsaitoh rv = -1; 1731.13Smsaitoh } 1741.13Smsaitoh } 1751.13Smsaitoherror: 1761.13Smsaitoh iic_release_bus(sc->sc_tag, 0); 1771.13Smsaitoh 1781.13Smsaitoh return rv; 1791.13Smsaitoh} 1801.13Smsaitoh 1811.16Sjakllschstatic const struct device_compatible_entry compat_data[] = { 1821.19Sthorpej { .compat = "atmel,spd" }, 1831.19Sthorpej { .compat = "i2c-at34c02" }, 1841.21Sthorpej DEVICE_COMPAT_EOL 1851.16Sjakllsch}; 1861.16Sjakllsch 1871.13Smsaitohstatic int 1881.1Spgoyettespdmem_i2c_match(device_t parent, cfdata_t match, void *aux) 1891.1Spgoyette{ 1901.1Spgoyette struct i2c_attach_args *ia = aux; 1911.1Spgoyette struct spdmem_i2c_softc sc; 1921.16Sjakllsch int match_result; 1931.16Sjakllsch 1941.16Sjakllsch if (iic_use_direct_match(ia, match, compat_data, &match_result)) 1951.16Sjakllsch return match_result; 1961.1Spgoyette 1971.15Sthorpej /* 1981.15Sthorpej * XXXJRT 1991.15Sthorpej * Should do this with "compatible" strings. There are also 2001.15Sthorpej * other problems with this "match" routine. Specifically, if 2011.15Sthorpej * we are doing direct-config, we know the device is already 2021.15Sthorpej * there aren't do need to probe. I'll leave the logic for 2031.15Sthorpej * now and let someone who knows better clean it later. 2041.15Sthorpej */ 2051.15Sthorpej 2061.1Spgoyette if (ia->ia_name) { 2071.1Spgoyette /* add other names as we find more firmware variations */ 2081.4Snakayama if (strcmp(ia->ia_name, "dimm-spd") && 2091.4Snakayama strcmp(ia->ia_name, "dimm")) 2101.1Spgoyette return 0; 2111.1Spgoyette } 2121.1Spgoyette 2131.1Spgoyette /* only do this lame test when not using direct config */ 2141.1Spgoyette if (ia->ia_name == NULL) { 2151.1Spgoyette if ((ia->ia_addr & SPDMEM_I2C_ADDRMASK) != SPDMEM_I2C_ADDR) 2161.1Spgoyette return 0; 2171.1Spgoyette } 2181.1Spgoyette 2191.1Spgoyette sc.sc_tag = ia->ia_tag; 2201.1Spgoyette sc.sc_addr = ia->ia_addr; 2211.11Smlelstv sc.sc_page0 = SPDCTL_SPA0; 2221.11Smlelstv sc.sc_page1 = SPDCTL_SPA1; 2231.1Spgoyette sc.sc_base.sc_read = spdmem_i2c_read; 2241.1Spgoyette 2251.13Smsaitoh /* Check the bank and reset to the page 0 */ 2261.13Smsaitoh if (spdmem_reset_page(&sc) != 0) 2271.13Smsaitoh return 0; 2281.13Smsaitoh 2291.15Sthorpej if (spdmem_common_probe(&sc.sc_base)) { 2301.15Sthorpej return ia->ia_name ? I2C_MATCH_DIRECT_SPECIFIC 2311.15Sthorpej : I2C_MATCH_ADDRESS_AND_PROBE; 2321.15Sthorpej } 2331.15Sthorpej return 0; 2341.1Spgoyette} 2351.1Spgoyette 2361.1Spgoyettestatic void 2371.1Spgoyettespdmem_i2c_attach(device_t parent, device_t self, void *aux) 2381.1Spgoyette{ 2391.1Spgoyette struct spdmem_i2c_softc *sc = device_private(self); 2401.1Spgoyette struct i2c_attach_args *ia = aux; 2411.1Spgoyette 2421.1Spgoyette sc->sc_tag = ia->ia_tag; 2431.1Spgoyette sc->sc_addr = ia->ia_addr; 2441.11Smlelstv sc->sc_page0 = SPDCTL_SPA0; 2451.11Smlelstv sc->sc_page1 = SPDCTL_SPA1; 2461.1Spgoyette sc->sc_base.sc_read = spdmem_i2c_read; 2471.1Spgoyette 2481.1Spgoyette if (!pmf_device_register(self, NULL, NULL)) 2491.1Spgoyette aprint_error_dev(self, "couldn't establish power handler\n"); 2501.1Spgoyette 2511.1Spgoyette spdmem_common_attach(&sc->sc_base, self); 2521.1Spgoyette} 2531.1Spgoyette 2541.2Spgoyettestatic int 2551.2Spgoyettespdmem_i2c_detach(device_t self, int flags) 2561.2Spgoyette{ 2571.2Spgoyette struct spdmem_i2c_softc *sc = device_private(self); 2581.2Spgoyette 2591.2Spgoyette pmf_device_deregister(self); 2601.2Spgoyette 2611.2Spgoyette return spdmem_common_detach(&sc->sc_base, self); 2621.2Spgoyette} 2631.2Spgoyette 2641.12Smsaitohstatic int 2651.12Smsaitohspdmem_i2c_read(struct spdmem_softc *softc, uint16_t addr, uint8_t *val) 2661.1Spgoyette{ 2671.12Smsaitoh uint8_t reg; 2681.1Spgoyette struct spdmem_i2c_softc *sc = (struct spdmem_i2c_softc *)softc; 2691.11Smlelstv static uint8_t dummy = 0; 2701.12Smsaitoh int rv; 2711.11Smlelstv 2721.11Smlelstv reg = addr & 0xff; 2731.1Spgoyette 2741.22Smlelstv rv = iic_acquire_bus(sc->sc_tag, 0); 2751.22Smlelstv if (rv) 2761.22Smlelstv return rv; 2771.11Smlelstv 2781.11Smlelstv if (addr & 0x100) { 2791.12Smsaitoh rv = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_page1, 2801.18Sthorpej &dummy, 1, &dummy, 1, 0); 2811.12Smsaitoh rv |= iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, 2821.18Sthorpej ®, 1, val, 1, 0); 2831.12Smsaitoh rv |= iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, 2841.18Sthorpej sc->sc_page0, &dummy, 1, &dummy, 1, 0); 2851.11Smlelstv } else { 2861.12Smsaitoh rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, 2871.18Sthorpej ®, 1, val, 1, 0); 2881.11Smlelstv } 2891.11Smlelstv 2901.1Spgoyette iic_release_bus(sc->sc_tag, 0); 2911.1Spgoyette 2921.12Smsaitoh return rv; 2931.1Spgoyette} 2941.2Spgoyette 2951.26SpgoyetteMODULE(MODULE_CLASS_DRIVER, spdmem, "iic"); 2961.2Spgoyette 2971.2Spgoyette#ifdef _MODULE 2981.2Spgoyette#include "ioconf.c" 2991.2Spgoyette#endif 3001.2Spgoyette 3011.2Spgoyettestatic int 3021.2Spgoyettespdmem_modcmd(modcmd_t cmd, void *opaque) 3031.2Spgoyette{ 3041.2Spgoyette int error = 0; 3051.5Spgoyette#ifdef _MODULE 3061.5Spgoyette static struct sysctllog *spdmem_sysctl_clog; 3071.5Spgoyette#endif 3081.2Spgoyette 3091.2Spgoyette switch (cmd) { 3101.2Spgoyette case MODULE_CMD_INIT: 3111.2Spgoyette#ifdef _MODULE 3121.2Spgoyette error = config_init_component(cfdriver_ioconf_spdmem, 3131.2Spgoyette cfattach_ioconf_spdmem, cfdata_ioconf_spdmem); 3141.2Spgoyette#endif 3151.2Spgoyette return error; 3161.2Spgoyette case MODULE_CMD_FINI: 3171.2Spgoyette#ifdef _MODULE 3181.2Spgoyette error = config_fini_component(cfdriver_ioconf_spdmem, 3191.2Spgoyette cfattach_ioconf_spdmem, cfdata_ioconf_spdmem); 3201.5Spgoyette sysctl_teardown(&spdmem_sysctl_clog); 3211.2Spgoyette#endif 3221.2Spgoyette return error; 3231.2Spgoyette default: 3241.2Spgoyette return ENOTTY; 3251.2Spgoyette } 3261.2Spgoyette} 327