ct65550reg.h revision 1.2.4.2
1 1.2.4.2 jruoho /* $NetBSD: ct65550reg.h,v 1.2.4.2 2011/06/06 09:07:52 jruoho Exp $ */ 2 1.2.4.2 jruoho 3 1.2.4.2 jruoho /* 4 1.2.4.2 jruoho * Copyright 2006 by Michael Lorenz. 5 1.2.4.2 jruoho * 6 1.2.4.2 jruoho * Redistribution and use in source and binary forms, with or without 7 1.2.4.2 jruoho * modification, are permitted provided that the following conditions 8 1.2.4.2 jruoho * are met: 9 1.2.4.2 jruoho * 1. Redistributions of source code must retain the above copyright 10 1.2.4.2 jruoho * notice, this list of conditions and the following disclaimer. 11 1.2.4.2 jruoho * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.4.2 jruoho * notice, this list of conditions and the following disclaimer in the 13 1.2.4.2 jruoho * documentation and/or other materials provided with the distribution. 14 1.2.4.2 jruoho * 15 1.2.4.2 jruoho * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.2.4.2 jruoho * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 1.2.4.2 jruoho * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 1.2.4.2 jruoho * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 1.2.4.2 jruoho * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 1.2.4.2 jruoho * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 1.2.4.2 jruoho * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 1.2.4.2 jruoho * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 1.2.4.2 jruoho * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 1.2.4.2 jruoho * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 1.2.4.2 jruoho * 26 1.2.4.2 jruoho */ 27 1.2.4.2 jruoho 28 1.2.4.2 jruoho #ifndef CHIPSFB_H 29 1.2.4.2 jruoho #define CHIPSFB_H 30 1.2.4.2 jruoho 31 1.2.4.2 jruoho /* VGA */ 32 1.2.4.2 jruoho #define CRTC_INDEX 0x3d4 33 1.2.4.2 jruoho #define CRTC_DATA 0x3d5 34 1.2.4.2 jruoho #define SEQ_INDEX 0x3c4 35 1.2.4.2 jruoho #define SEQ_DATA 0x3c5 36 1.2.4.2 jruoho #define MISC_W 0x3c2 37 1.2.4.2 jruoho #define GRA_INDEX 0x3ce 38 1.2.4.2 jruoho #define GRA_DATA 0x3cf 39 1.2.4.2 jruoho #define ATT_IW 0x3c0 40 1.2.4.2 jruoho 41 1.2.4.2 jruoho /* palette */ 42 1.2.4.2 jruoho #define CT_DACMASK 0x3c6 43 1.2.4.2 jruoho #define CT_DACSTATE 0x3c7 /* read only */ 44 1.2.4.2 jruoho #define CT_READINDEX 0x3c7 /* write only */ 45 1.2.4.2 jruoho #define CT_WRITEINDEX 0x3c8 46 1.2.4.2 jruoho #define CT_DACDATA 0x3c9 47 1.2.4.2 jruoho 48 1.2.4.2 jruoho /* extended VGA */ 49 1.2.4.2 jruoho #define CT_FP_INDEX 0x3d0 50 1.2.4.2 jruoho #define CT_FP_DATA 0x3d1 51 1.2.4.2 jruoho #define CT_MM_INDEX 0x3d2 52 1.2.4.2 jruoho #define CT_MM_DATA 0x3d3 53 1.2.4.2 jruoho #define CT_CONF_INDEX 0x3d6 54 1.2.4.2 jruoho #define CT_CONF_DATA 0x3d7 55 1.2.4.2 jruoho 56 1.2.4.2 jruoho /* offsets in aperture */ 57 1.2.4.2 jruoho #define CT_OFF_FB 0x00000000 58 1.2.4.2 jruoho #define CT_OFF_BITBLT 0x00400000 59 1.2.4.2 jruoho #define CT_OFF_DRAW 0x00400040 60 1.2.4.2 jruoho #define CT_OFF_DATA 0x00410000 61 1.2.4.2 jruoho 62 1.2.4.2 jruoho #define CT_OFF_BE 0x00800000 63 1.2.4.2 jruoho 64 1.2.4.2 jruoho /* blitter registers */ 65 1.2.4.2 jruoho #define CT_BLT_STRIDE 0x00000000 66 1.2.4.2 jruoho /* 67 1.2.4.2 jruoho * upper 16 bit are destination stride in bytes 68 1.2.4.2 jruoho * lower 16 bit are source stride in bytes 69 1.2.4.2 jruoho */ 70 1.2.4.2 jruoho 71 1.2.4.2 jruoho #define CT_BLT_BG 0x04 72 1.2.4.2 jruoho #define CT_BLT_FG 0x08 73 1.2.4.2 jruoho #define CT_BLT_EXPCTL 0x0c /* expansion control */ 74 1.2.4.2 jruoho #define LEFT_CLIPPING_MSK 0x0000003f 75 1.2.4.2 jruoho #define MONO_RIGHT_CLIPPING_MSK 0x00003f00 76 1.2.4.2 jruoho #define MONO_INITIAL_DISCARD 0x003f0000 77 1.2.4.2 jruoho #define MONO_SRC_ALIGN_MASK 0x07000000 78 1.2.4.2 jruoho #define MONO_SRC_ALIGN_BIT 0x01000000 79 1.2.4.2 jruoho #define MONO_SRC_ALIGN_BYTE 0x02000000 80 1.2.4.2 jruoho #define MONO_SRC_ALIGN_WORD 0x03000000 81 1.2.4.2 jruoho #define MONO_SRC_ALIGN_LONG 0x04000000 82 1.2.4.2 jruoho #define MONO_SRC_ALIGN_LONGLONG 0x05000000 83 1.2.4.2 jruoho #define MONO_SELECT_ALT_FG_BG 0x08000000 /* use CT_SRC_EXP_* */ 84 1.2.4.2 jruoho 85 1.2.4.2 jruoho #define CT_BLT_CONTROL 0x10 86 1.2.4.2 jruoho #define BLT_ROP_MASK 0x000000ff 87 1.2.4.2 jruoho #define BLT_START_RIGHT 0x00000100 /* 0 for start left */ 88 1.2.4.2 jruoho #define BLT_START_BOTTOM 0x00000200 /* 0 for start top */ 89 1.2.4.2 jruoho #define BLT_SRC_IS_CPU 0x00000400 /* 0 for vram source */ 90 1.2.4.2 jruoho #define BLT_SRC_IS_MONO 0x00001000 91 1.2.4.2 jruoho #define BLT_MONO_TRANSPARENCY 0x00002000 92 1.2.4.2 jruoho #define BLT_COLOR_COMPARE_MASK 0x0001c000 /* 0 for no color keying */ 93 1.2.4.2 jruoho #define BLT_PAT_TRANSPARENCY 0x00020000 /* pattern is transparent */ 94 1.2.4.2 jruoho #define BLT_PAT_IS_MONO 0x00040000 95 1.2.4.2 jruoho #define BLT_PAT_IS_SOLID 0x00080000 /* ignore pattern */ 96 1.2.4.2 jruoho #define BLT_PAT_VERT_ALIGN_MASK 0x00700000 97 1.2.4.2 jruoho #define BLT_IS_BUSY 0x80000000 98 1.2.4.2 jruoho 99 1.2.4.2 jruoho #define ROP_COPY 0xcc 100 1.2.4.2 jruoho #define ROP_NOT_SRC 0x33 101 1.2.4.2 jruoho #define ROP_NOT_DST 0x55 102 1.2.4.2 jruoho #define ROP_PAT 0xf0 103 1.2.4.2 jruoho 104 1.2.4.2 jruoho #define CT_BLT_PATTERN 0x14 /* address in vram */ 105 1.2.4.2 jruoho #define CT_BLT_SRCADDR 0x18 106 1.2.4.2 jruoho #define CT_BLT_DSTADDR 0x1c 107 1.2.4.2 jruoho 108 1.2.4.2 jruoho #define CT_BLT_SIZE 0x20 /* width and height */ 109 1.2.4.2 jruoho /* 110 1.2.4.2 jruoho * upper 16 bit are destination height 111 1.2.4.2 jruoho * lower 16 bit are destination width in bytes 112 1.2.4.2 jruoho */ 113 1.2.4.2 jruoho 114 1.2.4.2 jruoho #define CT_SRC_EXP_BG 0x24 115 1.2.4.2 jruoho #define CT_SRC_EXP_FG 0x28 116 1.2.4.2 jruoho 117 1.2.4.2 jruoho /* extension registers ( via CT_CONF */ 118 1.2.4.2 jruoho #define XR_VENDOR_LO 0x00 119 1.2.4.2 jruoho #define XR_VENDOR_HI 0x01 120 1.2.4.2 jruoho #define XR_DEVICE_LO 0x02 121 1.2.4.2 jruoho #define XR_DEVICE_HI 0x03 122 1.2.4.2 jruoho #define XR_REVISION 0x04 123 1.2.4.2 jruoho #define XR_LINEAR_BASE_LO 0x05 124 1.2.4.2 jruoho #define XR_LINEAR_BASE_HI 0x06 125 1.2.4.2 jruoho 126 1.2.4.2 jruoho #define XR_CONFIGURATION 0x08 127 1.2.4.2 jruoho #define BUS_PCI 0x01 128 1.2.4.2 jruoho #define BUS_VL 0x00 129 1.2.4.2 jruoho #define ENABLE_PCI 0x02 130 1.2.4.2 jruoho 131 1.2.4.2 jruoho #define XR_IO_CONTROL 0x09 132 1.2.4.2 jruoho #define ENABLE_CRTC_EXT 0x01 133 1.2.4.2 jruoho #define ENABLE_ATTR_EXT 0x02 134 1.2.4.2 jruoho 135 1.2.4.2 jruoho #define XR_ADDR_MAPPING 0x0a 136 1.2.4.2 jruoho #define ENABLE_MAPPING 0x01 /* in VGA window */ 137 1.2.4.2 jruoho #define ENABLE_LINEAR 0x02 138 1.2.4.2 jruoho #define ENABLE_PACKED 0x04 139 1.2.4.2 jruoho #define FB_SWAP_NONE 0x00 140 1.2.4.2 jruoho #define FB_SWAP_16 0x10 141 1.2.4.2 jruoho #define FB_SWAP_32 0x20 142 1.2.4.2 jruoho 143 1.2.4.2 jruoho #define XR_BURST_WRITE_MODE 0x0b 144 1.2.4.2 jruoho 145 1.2.4.2 jruoho #define XR_PAGE_SELECT 0x0e 146 1.2.4.2 jruoho 147 1.2.4.2 jruoho #define XR_BITBLT_CONTROL0 0x20 148 1.2.4.2 jruoho #define BLITTER_BUSY 0x01 149 1.2.4.2 jruoho #define BLITTER_RESET 0x02 150 1.2.4.2 jruoho #define BLITTER_8BIT 0x00 151 1.2.4.2 jruoho #define BLITTER_16BIT 0x10 152 1.2.4.2 jruoho #define BLITTER_24BIT 0x20 153 1.2.4.2 jruoho #define BLITTER_32BIT 0x30 /* reserved */ 154 1.2.4.2 jruoho 155 1.2.4.2 jruoho #define XR_DRAM_ACCESS_CONTROL 0x40 156 1.2.4.2 jruoho #define ENABLE_64BIT 0x01 157 1.2.4.2 jruoho #define DISABLE_WRAP 0x02 /* otherwise only 256kB */ 158 1.2.4.2 jruoho #define EXTENDED_TEXT 0x10 159 1.2.4.2 jruoho 160 1.2.4.2 jruoho #define XR_DRAM_TYPE 0x41 161 1.2.4.2 jruoho #define DRAM_FASTPAGE 0x00 162 1.2.4.2 jruoho #define DRAM_EDO 0x01 163 1.2.4.2 jruoho 164 1.2.4.2 jruoho #define XR_DRAM_CONFIG 0x42 165 1.2.4.2 jruoho #define DRAM_8BIT_COL 0x00 166 1.2.4.2 jruoho #define DRAM_9BIT_COL 0x01 167 1.2.4.2 jruoho 168 1.2.4.2 jruoho #define XR_DRAM_INTERFACE 0x43 169 1.2.4.2 jruoho #define XR_DRAM_TIMING 0x44 170 1.2.4.2 jruoho 171 1.2.4.2 jruoho #define XR_VIDEO_PIN_CONTROL 0x60 172 1.2.4.2 jruoho #define XR_DDC_SYNC_SELECT 0x61 173 1.2.4.2 jruoho #define DDC_HSYNC_DATA 0x01 174 1.2.4.2 jruoho #define DDC_HSYNC_OUT 0x02 /* hsync is controlled by above */ 175 1.2.4.2 jruoho #define DDC_VSYNC_DATA 0x04 176 1.2.4.2 jruoho #define DDC_VSYNC_OUT 0x08 /* vsync is controlled by above */ 177 1.2.4.2 jruoho #define DDC_HV_POWERDOWN 0x10 178 1.2.4.2 jruoho #define DDC_ENABLE_HSYNC 0x20 179 1.2.4.2 jruoho #define DDC_ENABLE_VSYNC 0x40 180 1.2.4.2 jruoho 181 1.2.4.2 jruoho /* 182 1.2.4.2 jruoho * upper 6 bit define if corresponding bits in DATA are input or output 183 1.2.4.2 jruoho * 1 selects output 184 1.2.4.2 jruoho */ 185 1.2.4.2 jruoho #define XR_GPIO_CONTROL 0x62 186 1.2.4.2 jruoho #define XR_GPIO_DATA 0x63 187 1.2.4.2 jruoho 188 1.2.4.2 jruoho #define XR_PIN_TRISTATE_CONTROL 0x67 189 1.2.4.2 jruoho 190 1.2.4.2 jruoho #define XR_CONFIG_PINS_0 0x70 191 1.2.4.2 jruoho #define XR_CONFIG_PINS_1 0x71 192 1.2.4.2 jruoho 193 1.2.4.2 jruoho #define XR_PIXEL_PIPELINE_CTL_0 0x80 194 1.2.4.2 jruoho #define ENABLE_EXTENDED_PALETTE 0x01 195 1.2.4.2 jruoho #define ENABLE_CRT_OVERSCAN 0x02 196 1.2.4.2 jruoho #define ENABLE_PANEL_OVERSCAN 0x04 197 1.2.4.2 jruoho #define ENABLE_EXTENDED_STATUS 0x08 198 1.2.4.2 jruoho #define ENABLE_CURSOR_1 0x10 199 1.2.4.2 jruoho #define ENABLE_PIXEL_AVERAGING 0x20 200 1.2.4.2 jruoho #define SELECT_PIXEL_STREAM 0x40 /* 1 for P1 */ 201 1.2.4.2 jruoho #define ENABLE_8BIT_DAC 0x80 /* 6 bit otherwise */ 202 1.2.4.2 jruoho 203 1.2.4.2 jruoho #define XR_PIXEL_PIPELINE_CTL_1 0x81 204 1.2.4.2 jruoho #define COLOR_VGA 0x00 205 1.2.4.2 jruoho #define COLOR_8BIT_EXTENDED 0x02 206 1.2.4.2 jruoho #define COLOR_15BIT 0x04 207 1.2.4.2 jruoho #define COLOR_16BIT 0x05 208 1.2.4.2 jruoho #define COLOR_24BIT 0x06 209 1.2.4.2 jruoho #define COLOR_32BIT 0x07 210 1.2.4.2 jruoho 211 1.2.4.2 jruoho #define XR_PIXEL_PIPELINE_CTL_2 0x82 212 1.2.4.2 jruoho #define ENABLE_BLANK_PEDESTAL 0x01 213 1.2.4.2 jruoho #define ENABLE_SYNC_ON_GREEN 0x02 214 1.2.4.2 jruoho #define ENABLE_VIDEO_GAMMA 0x04 215 1.2.4.2 jruoho #define ENABLE_GRAPHICS_GAMMA 0x08 216 1.2.4.2 jruoho 217 1.2.4.2 jruoho #define XR_CURSOR_1_CTL 0xa0 218 1.2.4.2 jruoho #define XR_CURSOR_1_VERT_EXT 0xa1 219 1.2.4.2 jruoho #define XR_CURSOR_1_BASEADDR_LO 0xa2 220 1.2.4.2 jruoho #define XR_CURSOR_1_BASEADDR_HI 0xa3 221 1.2.4.2 jruoho #define XR_CURSOR_1_X_LO 0xa4 222 1.2.4.2 jruoho #define XR_CURSOR_1_X_HI 0xa5 223 1.2.4.2 jruoho #define XR_CURSOR_1_Y_LO 0xa6 224 1.2.4.2 jruoho #define XR_CURSOR_1_Y_HI 0xa7 225 1.2.4.2 jruoho 226 1.2.4.2 jruoho #define XR_CURSOR_2_CTL 0xa8 227 1.2.4.2 jruoho #define XR_CURSOR_2_VERT_EXT 0xa9 228 1.2.4.2 jruoho #define XR_CURSOR_2_BASEADDR_LO 0xaa 229 1.2.4.2 jruoho #define XR_CURSOR_2_BASEADDR_HI 0xab 230 1.2.4.2 jruoho #define XR_CURSOR_2_X_LO 0xac 231 1.2.4.2 jruoho #define XR_CURSOR_2_X_HI 0xad 232 1.2.4.2 jruoho #define XR_CURSOR_2_Y_LO 0xae 233 1.2.4.2 jruoho #define XR_CURSOR_2_Y_HI 0xaf 234 1.2.4.2 jruoho 235 1.2.4.2 jruoho #define XR_VCLOCK_0_M 0xc0 236 1.2.4.2 jruoho #define XR_VCLOCK_0_N 0xc1 237 1.2.4.2 jruoho #define XR_VCLOCK_0_MN_MSBS 0xc2 238 1.2.4.2 jruoho #define XR_VCLOCK_0_DIV_SELECT 0xc3 239 1.2.4.2 jruoho 240 1.2.4.2 jruoho #define XR_VCLOCK_1_M 0xc4 241 1.2.4.2 jruoho #define XR_VCLOCK_1_N 0xc5 242 1.2.4.2 jruoho #define XR_VCLOCK_1_MN_MSBS 0xc6 243 1.2.4.2 jruoho #define XR_VCLOCK_1_DIV_SELECT 0xc7 244 1.2.4.2 jruoho 245 1.2.4.2 jruoho #define XR_VCLOCK_2_M 0xc8 246 1.2.4.2 jruoho #define XR_VCLOCK_2_N 0xc9 247 1.2.4.2 jruoho #define XR_VCLOCK_2_MN_MSBS 0xca 248 1.2.4.2 jruoho #define XR_VCLOCK_2_DIV_SELECT 0xcb 249 1.2.4.2 jruoho 250 1.2.4.2 jruoho #define XR_MEMCLOCK_M 0xcc 251 1.2.4.2 jruoho #define XR_MEMCLOCK_N 0xcd 252 1.2.4.2 jruoho #define XR_MEMCLOCK_DIV_SELECT 0xce 253 1.2.4.2 jruoho #define XR_CLOCK_CONFIG 0xcf 254 1.2.4.2 jruoho 255 1.2.4.2 jruoho #define XR_MODULE_POWER_DOWN 0xd0 256 1.2.4.2 jruoho #define XR_DOWN_COUNTER 0xd2 257 1.2.4.2 jruoho 258 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_0 0xe0 259 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_1 0xe1 260 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_2 0xe2 261 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_3 0xe3 262 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_4 0xe4 263 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_5 0xe5 264 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_6 0xe6 265 1.2.4.2 jruoho #define XR_SOFTWARE_FLAG_7 0xe7 266 1.2.4.2 jruoho 267 1.2.4.2 jruoho #define XR_TEST_BLOCK_SELECT 0xf8 268 1.2.4.2 jruoho #define XR_TEST_CONTROL_PORT 0xf9 269 1.2.4.2 jruoho #define XR_TEST_DATA_PORT 0xfa 270 1.2.4.2 jruoho #define XR_SCAN_TEST_CONTROL_0 0xfb 271 1.2.4.2 jruoho #define XR_SCAN_TEST_CONTROL_1 0xfc 272 1.2.4.2 jruoho 273 1.2.4.2 jruoho /* flat panel control registers, via CT_FP_* */ 274 1.2.4.2 jruoho #define FP_FEATURE 0x00 275 1.2.4.2 jruoho #define PANEL_EXISTS 0x01 276 1.2.4.2 jruoho #define POPUP_EXISTS 0x04 277 1.2.4.2 jruoho 278 1.2.4.2 jruoho #define FP_CRT_FP_CONTROL 0x01 279 1.2.4.2 jruoho #define ENABLE_CRT 0x01 280 1.2.4.2 jruoho #define ENABLE_PANEL 0x02 281 1.2.4.2 jruoho 282 1.2.4.2 jruoho #define FP_MODE_CONTROL 0x02 283 1.2.4.2 jruoho #define FP_DOT_CLOCK_SOURCE 0x03 284 1.2.4.2 jruoho #define FP_CLOCK_0 0x00 285 1.2.4.2 jruoho #define FP_CLOCK_1 0x04 286 1.2.4.2 jruoho #define FP_CLOCK_2 0x08 287 1.2.4.2 jruoho #define USE_VIDEO_CLOCK 0x00 288 1.2.4.2 jruoho #define USE_MEM_CLOCK 0x10 289 1.2.4.2 jruoho 290 1.2.4.2 jruoho #define FP_POWER_SEQ_DELAY 0x04 291 1.2.4.2 jruoho /* 292 1.2.4.2 jruoho * upper 4 bits select power up delay in 3.4ms increments 293 1.2.4.2 jruoho * lower 4 bits select power down delay in 29ms increments 294 1.2.4.2 jruoho */ 295 1.2.4.2 jruoho 296 1.2.4.2 jruoho #define FP_POWER_DOWN_CTL_1 0x05 297 1.2.4.2 jruoho /* the lower 3 bits select how many refresh cycles per scanline are preformed */ 298 1.2.4.2 jruoho #define PANEL_POWER_OFF 0x08 299 1.2.4.2 jruoho #define HOST_STANDBY 0x10 300 1.2.4.2 jruoho #define PANEL_TRISTATE 0x20 301 1.2.4.2 jruoho #define NO_SEFL_REFRESH 0x40 302 1.2.4.2 jruoho #define PANEL_INACTIVE 0x80 303 1.2.4.2 jruoho 304 1.2.4.2 jruoho /* these bits are effective when the panel is powered down */ 305 1.2.4.2 jruoho #define FP_POWER_DOWN_CTL_0 0x06 306 1.2.4.2 jruoho #define FP_VGA_PALETTE_POWERDOWN 0x01 307 1.2.4.2 jruoho #define FP_VGA_PALETTE_ENABLE 0x02 308 1.2.4.2 jruoho #define FP_ENABLE_SYNC 0x04 309 1.2.4.2 jruoho 310 1.2.4.2 jruoho #define FP_PIN_POLARITY 0x08 311 1.2.4.2 jruoho #define FP_DISPLAY_NEGATIVE 0x02 312 1.2.4.2 jruoho #define FP_HSYNC_NEGATIVE 0x04 313 1.2.4.2 jruoho #define FP_VSYNC_NEGATIVE 0x08 314 1.2.4.2 jruoho #define FP_TEXT_VIDEO_INVERT 0x10 315 1.2.4.2 jruoho #define FP_GRAPHICS_INVERT 0x20 316 1.2.4.2 jruoho #define CRT_HSYNC_NEGATIVE 0x40 317 1.2.4.2 jruoho #define CRT_VSYNC_NEGATIVE 0x80 318 1.2.4.2 jruoho 319 1.2.4.2 jruoho #define FP_OUTPUT_DRIVE 0x0a 320 1.2.4.2 jruoho #define VL_THRESHOLD_5V 0x02 /* 3.3v otherwise */ 321 1.2.4.2 jruoho #define FP_DRIVE_HIGH 0x04 /* req. with 3.3v */ 322 1.2.4.2 jruoho #define BUS_INTERFACE_LOW 0x08 /* req. with 3.3v */ 323 1.2.4.2 jruoho #define MEM_DRIVE_HIGHER 0x10 324 1.2.4.2 jruoho #define MEM_C_DRIVE_HIGHER 0x20 325 1.2.4.2 jruoho #define SYNC_DRIVE_HIGHER 0x40 326 1.2.4.2 jruoho 327 1.2.4.2 jruoho #define FP_PIN_CONTROL_1 0x0b 328 1.2.4.2 jruoho #define DISPLAY_ENABLE_ON_69 0x01 /* M signal otherwise */ 329 1.2.4.2 jruoho #define DISPLAY_ENABLE_ON_68 0x02 /* FP Hsync otherwise */ 330 1.2.4.2 jruoho #define COMPOSITE_SYNC_ON_65 0x04 /* separate otherwise */ 331 1.2.4.2 jruoho #define BACKLIGHT_ON_61 0x08 /* on 54 otherwise */ 332 1.2.4.2 jruoho #define GPIO_ON_154 0x10 333 1.2.4.2 jruoho #define SIMPLE_COMPOSITE_SYNC 0x20 334 1.2.4.2 jruoho #define MEM_C_TRISTATE 0x80 335 1.2.4.2 jruoho 336 1.2.4.2 jruoho #define FP_PIN_CONTROL_2 0x0c 337 1.2.4.2 jruoho #define ACTI_ON_53 0x00 338 1.2.4.2 jruoho #define COMPOSITE_SYNC_ON_53 0x08 339 1.2.4.2 jruoho #define GPIO_IN_ON_53 0x10 340 1.2.4.2 jruoho #define GPIO_OUT_ON_53 0x18 341 1.2.4.2 jruoho #define ENABKL_ON_54 0x00 342 1.2.4.2 jruoho #define COMPOSITE_SYNC_ON_54 0x40 343 1.2.4.2 jruoho #define GPIO_IN_ON_54 0x80 344 1.2.4.2 jruoho #define GPIO_OUT_ON_54 0xc0 345 1.2.4.2 jruoho 346 1.2.4.2 jruoho #define FP_ACTIVITY_CONTROL 0x0f 347 1.2.4.2 jruoho /* the lower 5 bits select a timeout in 28.1s increments */ 348 1.2.4.2 jruoho #define PANEL_OFF_ON_TIMEOUT 0x40 /* backlight off otherwise */ 349 1.2.4.2 jruoho #define ENABLE_ACTIVITY_TIMER 0x80 350 1.2.4.2 jruoho 351 1.2.4.2 jruoho #define FP_PANEL_FORMAT_0 0x10 352 1.2.4.2 jruoho #define SINGLE_PANEL_SINGLE_DRIVE 0x00 353 1.2.4.2 jruoho #define DUAL_PANEL_DUAL_DRIVE 0x03 354 1.2.4.2 jruoho #define MONO_NTSC 0x00 355 1.2.4.2 jruoho #define MONO_EQUIV_WEIGHT 0x04 356 1.2.4.2 jruoho #define MONO_GREEN_ONLY 0x08 357 1.2.4.2 jruoho #define COLOUR_PANEL 0x0c 358 1.2.4.2 jruoho #define SHIFT_CLOCK_DIVIDER_MASK 0x70 359 1.2.4.2 jruoho 360 1.2.4.2 jruoho #define FP_PANEL_FORMAT_1 0x11 361 1.2.4.2 jruoho 362 1.2.4.2 jruoho #define FP_PANEL_FORMAT_2 0x12 363 1.2.4.2 jruoho #define FP_PANEL_FORMAT_3 0x13 364 1.2.4.2 jruoho 365 1.2.4.2 jruoho #define FP_FRC_OPTION_SELECT 0x16 366 1.2.4.2 jruoho #define FP_POLYNOMIAL_FRC_CTL 0x17 367 1.2.4.2 jruoho 368 1.2.4.2 jruoho #define FP_TEXTMODE_CONTROL 0x18 369 1.2.4.2 jruoho #define FP_BLINK_RATE_CONTROL 0x19 370 1.2.4.2 jruoho #define FP_FB_CONTROL 0x1a 371 1.2.4.2 jruoho 372 1.2.4.2 jruoho #define FP_ACDCLK_CONTROL 0x1e 373 1.2.4.2 jruoho #define FP_DIAGNOSTIC 0x1f 374 1.2.4.2 jruoho 375 1.2.4.2 jruoho #define FP_HSIZE_LSB 0x20 /* panel size - 1 */ 376 1.2.4.2 jruoho #define FP_HSYNC_START 0x21 /* value - 1 */ 377 1.2.4.2 jruoho #define FP_HSYNC_END 0x22 378 1.2.4.2 jruoho #define FP_HTOTAL_LSB 0x23 /* value - 5 */ 379 1.2.4.2 jruoho #define FP_HSYNC_DELAY_LSB 0x24 380 1.2.4.2 jruoho #define FP_HORZ_OVERFLOW_1 0x25 381 1.2.4.2 jruoho /* 382 1.2.4.2 jruoho * upper 4 bits are upper 4 bits of FP_HSYNC_START 383 1.2.4.2 jruoho * lower 4 bits are upper 4 bits of FP_HSIZE_LSB 384 1.2.4.2 jruoho */ 385 1.2.4.2 jruoho 386 1.2.4.2 jruoho #define FP_HORZ_OVERFLOW_2 0x26 387 1.2.4.2 jruoho /* 388 1.2.4.2 jruoho * upper 4 bits are upper 4 bits of FP_HSYNC_DELAY_LSB 389 1.2.4.2 jruoho * lower 4 bits are upper 4 bits of FP_HTOTAL_LSB 390 1.2.4.2 jruoho */ 391 1.2.4.2 jruoho 392 1.2.4.2 jruoho #define FP_HSYNC_WIDTH_DISABLE 0x27 393 1.2.4.2 jruoho /* lower 7 bits are HSYNC width - 1 */ 394 1.2.4.2 jruoho #define DELAY_DISABLE 0x80 395 1.2.4.2 jruoho 396 1.2.4.2 jruoho #define FP_VSIZE_LSB 0x30 /* panel size - 1 */ 397 1.2.4.2 jruoho #define FP_VSYNC_START 0x31 /* value - 1 */ 398 1.2.4.2 jruoho #define FP_VSYNC_END 0x32 /* value - 1 */ 399 1.2.4.2 jruoho #define FP_VTOTAL_LSB 0x33 /* value - 2 */ 400 1.2.4.2 jruoho #define FP_VSYNC_DELAY_LSB 0x34 /* value - 1 */ 401 1.2.4.2 jruoho #define FP_VERT_OVERFLOW_1 0x35 402 1.2.4.2 jruoho /* 403 1.2.4.2 jruoho * upper 4 bits are upper 4 bits of FP_VSYNC_START 404 1.2.4.2 jruoho * lower 4 bits are upper 4 bits of FP_VSIZE_LSB 405 1.2.4.2 jruoho */ 406 1.2.4.2 jruoho 407 1.2.4.2 jruoho #define FP_VERT_OVERFLOW_2 0x36 408 1.2.4.2 jruoho /* 409 1.2.4.2 jruoho * upper 4 bits are upper 4 bits of FP_VSYNC_DELAY_LSB 410 1.2.4.2 jruoho * lower 4 bits are upper 4 bits of FP_VTOTAL_LSB 411 1.2.4.2 jruoho */ 412 1.2.4.2 jruoho 413 1.2.4.2 jruoho #define FP_VSYNC_DISABLE 0x37 414 1.2.4.2 jruoho #define FP_VSYNC_WIDTH_MASK 0x38 /* value - 1 */ 415 1.2.4.2 jruoho #define FP_VSYNC_IS_CRT_VSYNC 0x40 416 1.2.4.2 jruoho #define FP_VSYNC_DELAY_DISABLE 0x80 417 1.2.4.2 jruoho 418 1.2.4.2 jruoho #define FP_HORZ_COMPENSATION 0x40 419 1.2.4.2 jruoho #define FP_VERT_COMPENSATION 0x41 420 1.2.4.2 jruoho #define FP_VERT_COMPENSATION2 0x48 421 1.2.4.2 jruoho 422 1.2.4.2 jruoho #define FP_TEXT_VSTRETCH_0_MSB 0x49 423 1.2.4.2 jruoho #define FP_TEXT_VSTRETCH_0_LSB 0x4a 424 1.2.4.2 jruoho #define FP_TEXT_VSTRETCH_1_MSB 0x4b 425 1.2.4.2 jruoho #define FP_TEXT_VSTRETCH_1_LSB 0x4c 426 1.2.4.2 jruoho #define FP_TEXT_LINE_REPL 0x4d 427 1.2.4.2 jruoho #define FP_SEL_VSTRETCH_DISABLE 0x4e 428 1.2.4.2 jruoho 429 1.2.4.2 jruoho 430 1.2.4.2 jruoho 431 1.2.4.2 jruoho #endif 432
Indexes created Sat Nov 01 21:09:44 GMT 2025