Home | History | Annotate | Line # | Download | only in ic
gem.c revision 1.102
      1 /*	$NetBSD$ */
      2 
      3 /*
      4  *
      5  * Copyright (C) 2001 Eduardo Horvath.
      6  * Copyright (c) 2001-2003 Thomas Moestl
      7  * All rights reserved.
      8  *
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
     20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
     23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  *
     31  */
     32 
     33 /*
     34  * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
     35  * See `GEM Gigabit Ethernet ASIC Specification'
     36  *   http://www.sun.com/processors/manuals/ge.pdf
     37  */
     38 
     39 #include <sys/cdefs.h>
     40 __KERNEL_RCSID(0, "$NetBSD$");
     41 
     42 #include "opt_inet.h"
     43 
     44 #include <sys/param.h>
     45 #include <sys/systm.h>
     46 #include <sys/callout.h>
     47 #include <sys/mbuf.h>
     48 #include <sys/syslog.h>
     49 #include <sys/malloc.h>
     50 #include <sys/kernel.h>
     51 #include <sys/socket.h>
     52 #include <sys/ioctl.h>
     53 #include <sys/errno.h>
     54 #include <sys/device.h>
     55 
     56 #include <machine/endian.h>
     57 
     58 #include <net/if.h>
     59 #include <net/if_dl.h>
     60 #include <net/if_media.h>
     61 #include <net/if_ether.h>
     62 
     63 #ifdef INET
     64 #include <netinet/in.h>
     65 #include <netinet/in_systm.h>
     66 #include <netinet/in_var.h>
     67 #include <netinet/ip.h>
     68 #include <netinet/tcp.h>
     69 #include <netinet/udp.h>
     70 #endif
     71 
     72 #include <net/bpf.h>
     73 
     74 #include <sys/bus.h>
     75 #include <sys/intr.h>
     76 
     77 #include <dev/mii/mii.h>
     78 #include <dev/mii/miivar.h>
     79 #include <dev/mii/mii_bitbang.h>
     80 
     81 #include <dev/ic/gemreg.h>
     82 #include <dev/ic/gemvar.h>
     83 
     84 #define TRIES	10000
     85 
     86 static void	gem_inten(struct gem_softc *);
     87 static void	gem_start(struct ifnet *);
     88 static void	gem_stop(struct ifnet *, int);
     89 int		gem_ioctl(struct ifnet *, u_long, void *);
     90 void		gem_tick(void *);
     91 void		gem_watchdog(struct ifnet *);
     92 void		gem_rx_watchdog(void *);
     93 void		gem_pcs_start(struct gem_softc *sc);
     94 void		gem_pcs_stop(struct gem_softc *sc, int);
     95 int		gem_init(struct ifnet *);
     96 void		gem_init_regs(struct gem_softc *sc);
     97 static int	gem_ringsize(int sz);
     98 static int	gem_meminit(struct gem_softc *);
     99 void		gem_mifinit(struct gem_softc *);
    100 static int	gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int,
    101 		    u_int32_t, u_int32_t);
    102 void		gem_reset(struct gem_softc *);
    103 int		gem_reset_rx(struct gem_softc *sc);
    104 static void	gem_reset_rxdma(struct gem_softc *sc);
    105 static void	gem_rx_common(struct gem_softc *sc);
    106 int		gem_reset_tx(struct gem_softc *sc);
    107 int		gem_disable_rx(struct gem_softc *sc);
    108 int		gem_disable_tx(struct gem_softc *sc);
    109 static void	gem_rxdrain(struct gem_softc *sc);
    110 int		gem_add_rxbuf(struct gem_softc *sc, int idx);
    111 void		gem_setladrf(struct gem_softc *);
    112 
    113 /* MII methods & callbacks */
    114 static int	gem_mii_readreg(device_t, int, int);
    115 static void	gem_mii_writereg(device_t, int, int, int);
    116 static void	gem_mii_statchg(struct ifnet *);
    117 
    118 static int	gem_ifflags_cb(struct ethercom *);
    119 
    120 void		gem_statuschange(struct gem_softc *);
    121 
    122 int		gem_ser_mediachange(struct ifnet *);
    123 void		gem_ser_mediastatus(struct ifnet *, struct ifmediareq *);
    124 
    125 static void	gem_partial_detach(struct gem_softc *, enum gem_attach_stage);
    126 
    127 struct mbuf	*gem_get(struct gem_softc *, int, int);
    128 int		gem_put(struct gem_softc *, int, struct mbuf *);
    129 void		gem_read(struct gem_softc *, int, int);
    130 int		gem_pint(struct gem_softc *);
    131 int		gem_eint(struct gem_softc *, u_int);
    132 int		gem_rint(struct gem_softc *);
    133 int		gem_tint(struct gem_softc *);
    134 void		gem_power(int, void *);
    135 
    136 #ifdef GEM_DEBUG
    137 static void gem_txsoft_print(const struct gem_softc *, int, int);
    138 #define	DPRINTF(sc, x)	if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \
    139 				printf x
    140 #else
    141 #define	DPRINTF(sc, x)	/* nothing */
    142 #endif
    143 
    144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header))
    145 
    146 int
    147 gem_detach(struct gem_softc *sc, int flags)
    148 {
    149 	int i;
    150 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    151 	bus_space_tag_t t = sc->sc_bustag;
    152 	bus_space_handle_t h = sc->sc_h1;
    153 
    154 	/*
    155 	 * Free any resources we've allocated during the attach.
    156 	 * Do this in reverse order and fall through.
    157 	 */
    158 	switch (sc->sc_att_stage) {
    159 	case GEM_ATT_BACKEND_2:
    160 	case GEM_ATT_BACKEND_1:
    161 	case GEM_ATT_FINISHED:
    162 		bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0);
    163 		gem_stop(&sc->sc_ethercom.ec_if, 1);
    164 
    165 #ifdef GEM_COUNTERS
    166 		for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; )
    167 			evcnt_detach(&sc->sc_ev_rxhist[i]);
    168 		evcnt_detach(&sc->sc_ev_rxnobuf);
    169 		evcnt_detach(&sc->sc_ev_rxfull);
    170 		evcnt_detach(&sc->sc_ev_rxint);
    171 		evcnt_detach(&sc->sc_ev_txint);
    172 #endif
    173 		evcnt_detach(&sc->sc_ev_intr);
    174 
    175 		rnd_detach_source(&sc->rnd_source);
    176 		ether_ifdetach(ifp);
    177 		if_detach(ifp);
    178 		ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
    179 
    180 		callout_destroy(&sc->sc_tick_ch);
    181 		callout_destroy(&sc->sc_rx_watchdog);
    182 
    183 		/*FALLTHROUGH*/
    184 	case GEM_ATT_MII:
    185 		sc->sc_att_stage = GEM_ATT_MII;
    186 		mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
    187 		/*FALLTHROUGH*/
    188 	case GEM_ATT_7:
    189 		for (i = 0; i < GEM_NRXDESC; i++) {
    190 			if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
    191 				bus_dmamap_destroy(sc->sc_dmatag,
    192 				    sc->sc_rxsoft[i].rxs_dmamap);
    193 		}
    194 		/*FALLTHROUGH*/
    195 	case GEM_ATT_6:
    196 		for (i = 0; i < GEM_TXQUEUELEN; i++) {
    197 			if (sc->sc_txsoft[i].txs_dmamap != NULL)
    198 				bus_dmamap_destroy(sc->sc_dmatag,
    199 				    sc->sc_txsoft[i].txs_dmamap);
    200 		}
    201 		bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap);
    202 		/*FALLTHROUGH*/
    203 	case GEM_ATT_5:
    204 		bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap);
    205 		/*FALLTHROUGH*/
    206 	case GEM_ATT_4:
    207 		bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap);
    208 		/*FALLTHROUGH*/
    209 	case GEM_ATT_3:
    210 		bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap);
    211 		/*FALLTHROUGH*/
    212 	case GEM_ATT_2:
    213 		bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data,
    214 		    sizeof(struct gem_control_data));
    215 		/*FALLTHROUGH*/
    216 	case GEM_ATT_1:
    217 		bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg);
    218 		/*FALLTHROUGH*/
    219 	case GEM_ATT_0:
    220 		sc->sc_att_stage = GEM_ATT_0;
    221 		/*FALLTHROUGH*/
    222 	case GEM_ATT_BACKEND_0:
    223 		break;
    224 	}
    225 	return 0;
    226 }
    227 
    228 static void
    229 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage)
    230 {
    231 	cfattach_t ca = device_cfattach(sc->sc_dev);
    232 
    233 	sc->sc_att_stage = stage;
    234 	(*ca->ca_detach)(sc->sc_dev, 0);
    235 }
    236 
    237 /*
    238  * gem_attach:
    239  *
    240  *	Attach a Gem interface to the system.
    241  */
    242 void
    243 gem_attach(struct gem_softc *sc, const uint8_t *enaddr)
    244 {
    245 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    246 	struct mii_data *mii = &sc->sc_mii;
    247 	bus_space_tag_t t = sc->sc_bustag;
    248 	bus_space_handle_t h = sc->sc_h1;
    249 	struct ifmedia_entry *ifm;
    250 	int i, error, phyaddr;
    251 	u_int32_t v;
    252 	char *nullbuf;
    253 
    254 	/* Make sure the chip is stopped. */
    255 	ifp->if_softc = sc;
    256 	gem_reset(sc);
    257 
    258 	/*
    259 	 * Allocate the control data structures, and create and load the
    260 	 * DMA map for it. gem_control_data is 9216 bytes, we have space for
    261 	 * the padding buffer in the bus_dmamem_alloc()'d memory.
    262 	 */
    263 	if ((error = bus_dmamem_alloc(sc->sc_dmatag,
    264 	    sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE,
    265 	    0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) {
    266 		aprint_error_dev(sc->sc_dev,
    267 		   "unable to allocate control data, error = %d\n",
    268 		    error);
    269 		gem_partial_detach(sc, GEM_ATT_0);
    270 		return;
    271 	}
    272 
    273 	/* XXX should map this in with correct endianness */
    274 	if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg,
    275 	    sizeof(struct gem_control_data), (void **)&sc->sc_control_data,
    276 	    BUS_DMA_COHERENT)) != 0) {
    277 		aprint_error_dev(sc->sc_dev,
    278 		    "unable to map control data, error = %d\n", error);
    279 		gem_partial_detach(sc, GEM_ATT_1);
    280 		return;
    281 	}
    282 
    283 	nullbuf =
    284 	    (char *)sc->sc_control_data + sizeof(struct gem_control_data);
    285 
    286 	if ((error = bus_dmamap_create(sc->sc_dmatag,
    287 	    sizeof(struct gem_control_data), 1,
    288 	    sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
    289 		aprint_error_dev(sc->sc_dev,
    290 		    "unable to create control data DMA map, error = %d\n",
    291 		    error);
    292 		gem_partial_detach(sc, GEM_ATT_2);
    293 		return;
    294 	}
    295 
    296 	if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap,
    297 	    sc->sc_control_data, sizeof(struct gem_control_data), NULL,
    298 	    0)) != 0) {
    299 		aprint_error_dev(sc->sc_dev,
    300 		    "unable to load control data DMA map, error = %d\n",
    301 		    error);
    302 		gem_partial_detach(sc, GEM_ATT_3);
    303 		return;
    304 	}
    305 
    306 	memset(nullbuf, 0, ETHER_MIN_TX);
    307 	if ((error = bus_dmamap_create(sc->sc_dmatag,
    308 	    ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) {
    309 		aprint_error_dev(sc->sc_dev,
    310 		    "unable to create padding DMA map, error = %d\n", error);
    311 		gem_partial_detach(sc, GEM_ATT_4);
    312 		return;
    313 	}
    314 
    315 	if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap,
    316 	    nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) {
    317 		aprint_error_dev(sc->sc_dev,
    318 		    "unable to load padding DMA map, error = %d\n", error);
    319 		gem_partial_detach(sc, GEM_ATT_5);
    320 		return;
    321 	}
    322 
    323 	bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX,
    324 	    BUS_DMASYNC_PREWRITE);
    325 
    326 	/*
    327 	 * Initialize the transmit job descriptors.
    328 	 */
    329 	SIMPLEQ_INIT(&sc->sc_txfreeq);
    330 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
    331 
    332 	/*
    333 	 * Create the transmit buffer DMA maps.
    334 	 */
    335 	for (i = 0; i < GEM_TXQUEUELEN; i++) {
    336 		struct gem_txsoft *txs;
    337 
    338 		txs = &sc->sc_txsoft[i];
    339 		txs->txs_mbuf = NULL;
    340 		if ((error = bus_dmamap_create(sc->sc_dmatag,
    341 		    ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS,
    342 		    ETHER_MAX_LEN_JUMBO, 0, 0,
    343 		    &txs->txs_dmamap)) != 0) {
    344 			aprint_error_dev(sc->sc_dev,
    345 			    "unable to create tx DMA map %d, error = %d\n",
    346 			    i, error);
    347 			gem_partial_detach(sc, GEM_ATT_6);
    348 			return;
    349 		}
    350 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
    351 	}
    352 
    353 	/*
    354 	 * Create the receive buffer DMA maps.
    355 	 */
    356 	for (i = 0; i < GEM_NRXDESC; i++) {
    357 		if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
    358 		    MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
    359 			aprint_error_dev(sc->sc_dev,
    360 			    "unable to create rx DMA map %d, error = %d\n",
    361 			    i, error);
    362 			gem_partial_detach(sc, GEM_ATT_7);
    363 			return;
    364 		}
    365 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
    366 	}
    367 
    368 	/* Initialize ifmedia structures and MII info */
    369 	mii->mii_ifp = ifp;
    370 	mii->mii_readreg = gem_mii_readreg;
    371 	mii->mii_writereg = gem_mii_writereg;
    372 	mii->mii_statchg = gem_mii_statchg;
    373 
    374 	sc->sc_ethercom.ec_mii = mii;
    375 
    376 	/*
    377 	 * Initialization based  on `GEM Gigabit Ethernet ASIC Specification'
    378 	 * Section 3.2.1 `Initialization Sequence'.
    379 	 * However, we can't assume SERDES or Serialink if neither
    380 	 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set
    381 	 * being set, as both are set on Sun X1141A (with SERDES).  So,
    382 	 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL.
    383 	 * Also, for variants that report 2 PHY's, we prefer the external
    384 	 * PHY over the internal PHY, so we look for that first.
    385 	 */
    386 	gem_mifinit(sc);
    387 
    388 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) {
    389 		ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
    390 		    ether_mediastatus);
    391 		/* Look for external PHY */
    392 		if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
    393 			sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
    394 			bus_space_write_4(t, h, GEM_MIF_CONFIG,
    395 			    sc->sc_mif_config);
    396 			switch (sc->sc_variant) {
    397 			case GEM_SUN_ERI:
    398 				phyaddr = GEM_PHYAD_EXTERNAL;
    399 				break;
    400 			default:
    401 				phyaddr = MII_PHY_ANY;
    402 				break;
    403 			}
    404 			mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr,
    405 			    MII_OFFSET_ANY, MIIF_FORCEANEG);
    406 		}
    407 #ifdef GEM_DEBUG
    408 		  else
    409 			aprint_debug_dev(sc->sc_dev, "using external PHY\n");
    410 #endif
    411 		/* Look for internal PHY if no external PHY was found */
    412 		if (LIST_EMPTY(&mii->mii_phys) &&
    413 		    sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) {
    414 			sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
    415 			bus_space_write_4(t, h, GEM_MIF_CONFIG,
    416 			    sc->sc_mif_config);
    417 			switch (sc->sc_variant) {
    418 			case GEM_SUN_ERI:
    419 			case GEM_APPLE_K2_GMAC:
    420 				phyaddr = GEM_PHYAD_INTERNAL;
    421 				break;
    422 			case GEM_APPLE_GMAC:
    423 				phyaddr = GEM_PHYAD_EXTERNAL;
    424 				break;
    425 			default:
    426 				phyaddr = MII_PHY_ANY;
    427 				break;
    428 			}
    429 			mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr,
    430 			    MII_OFFSET_ANY, MIIF_FORCEANEG);
    431 #ifdef GEM_DEBUG
    432 			if (!LIST_EMPTY(&mii->mii_phys))
    433 				aprint_debug_dev(sc->sc_dev,
    434 				    "using internal PHY\n");
    435 #endif
    436 		}
    437 		if (LIST_EMPTY(&mii->mii_phys)) {
    438 				/* No PHY attached */
    439 				aprint_error_dev(sc->sc_dev,
    440 				    "PHY probe failed\n");
    441 				gem_partial_detach(sc, GEM_ATT_MII);
    442 				return;
    443 		} else {
    444 			struct mii_softc *child;
    445 
    446 			/*
    447 			 * Walk along the list of attached MII devices and
    448 			 * establish an `MII instance' to `PHY number'
    449 			 * mapping.
    450 			 */
    451 			LIST_FOREACH(child, &mii->mii_phys, mii_list) {
    452 				/*
    453 				 * Note: we support just one PHY: the internal
    454 				 * or external MII is already selected for us
    455 				 * by the GEM_MIF_CONFIG  register.
    456 				 */
    457 				if (child->mii_phy > 1 || child->mii_inst > 0) {
    458 					aprint_error_dev(sc->sc_dev,
    459 					    "cannot accommodate MII device"
    460 					    " %s at PHY %d, instance %d\n",
    461 					       device_xname(child->mii_dev),
    462 					       child->mii_phy, child->mii_inst);
    463 					continue;
    464 				}
    465 				sc->sc_phys[child->mii_inst] = child->mii_phy;
    466 			}
    467 
    468 			if (sc->sc_variant != GEM_SUN_ERI)
    469 				bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    470 				    GEM_MII_DATAPATH_MII);
    471 
    472 			/*
    473 			 * XXX - we can really do the following ONLY if the
    474 			 * PHY indeed has the auto negotiation capability!!
    475 			 */
    476 			ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
    477 		}
    478 	} else {
    479 		ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange,
    480 		    gem_ser_mediastatus);
    481 		/* SERDES or Serialink */
    482 		if (sc->sc_flags & GEM_SERDES) {
    483 			bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    484 			    GEM_MII_DATAPATH_SERDES);
    485 		} else {
    486 			sc->sc_flags |= GEM_SERIAL;
    487 			bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    488 			    GEM_MII_DATAPATH_SERIAL);
    489 		}
    490 
    491 		aprint_normal_dev(sc->sc_dev, "using external PCS %s: ",
    492 		    sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink");
    493 
    494 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL);
    495 		/* Check for FDX and HDX capabilities */
    496 		sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR);
    497 		if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) {
    498 			ifmedia_add(&sc->sc_mii.mii_media,
    499 			    IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL);
    500 			aprint_normal("1000baseSX-FDX, ");
    501 		}
    502 		if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) {
    503 			ifmedia_add(&sc->sc_mii.mii_media,
    504 			    IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL);
    505 			aprint_normal("1000baseSX-HDX, ");
    506 		}
    507 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
    508 		sc->sc_mii_media = IFM_AUTO;
    509 		aprint_normal("auto\n");
    510 
    511 		gem_pcs_stop(sc, 1);
    512 	}
    513 
    514 	/*
    515 	 * From this point forward, the attachment cannot fail.  A failure
    516 	 * before this point releases all resources that may have been
    517 	 * allocated.
    518 	 */
    519 
    520 	/* Announce ourselves. */
    521 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s",
    522 	    ether_sprintf(enaddr));
    523 
    524 	/* Get RX FIFO size */
    525 	sc->sc_rxfifosize = 64 *
    526 	    bus_space_read_4(t, h, GEM_RX_FIFO_SIZE);
    527 	aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024);
    528 
    529 	/* Get TX FIFO size */
    530 	v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE);
    531 	aprint_normal(", %uKB TX fifo\n", v / 16);
    532 
    533 	/* Initialize ifnet structure. */
    534 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
    535 	ifp->if_softc = sc;
    536 	ifp->if_flags =
    537 	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
    538 	sc->sc_if_flags = ifp->if_flags;
    539 #if 0
    540 	/*
    541 	 * The GEM hardware supports basic TCP checksum offloading only.
    542 	 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80)
    543 	 * have bugs in the receive checksum, so don't enable it for now.
    544 	 */
    545 	if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) ||
    546 	    (GEM_IS_APPLE(sc) &&
    547 	    (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80)))
    548 		ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx;
    549 #endif
    550 	ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx;
    551 	ifp->if_start = gem_start;
    552 	ifp->if_ioctl = gem_ioctl;
    553 	ifp->if_watchdog = gem_watchdog;
    554 	ifp->if_stop = gem_stop;
    555 	ifp->if_init = gem_init;
    556 	IFQ_SET_READY(&ifp->if_snd);
    557 
    558 	/*
    559 	 * If we support GigE media, we support jumbo frames too.
    560 	 * Unless we are Apple.
    561 	 */
    562 	TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) {
    563 		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T ||
    564 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX ||
    565 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX ||
    566 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) {
    567 			if (!GEM_IS_APPLE(sc))
    568 				sc->sc_ethercom.ec_capabilities
    569 				    |= ETHERCAP_JUMBO_MTU;
    570 			sc->sc_flags |= GEM_GIGABIT;
    571 			break;
    572 		}
    573 	}
    574 
    575 	/* claim 802.1q capability */
    576 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
    577 
    578 	/* Attach the interface. */
    579 	if_attach(ifp);
    580 	ether_ifattach(ifp, enaddr);
    581 	ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb);
    582 
    583 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
    584 			  RND_TYPE_NET, RND_FLAG_DEFAULT);
    585 
    586 	evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR,
    587 	    NULL, device_xname(sc->sc_dev), "interrupts");
    588 #ifdef GEM_COUNTERS
    589 	evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR,
    590 	    &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts");
    591 	evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR,
    592 	    &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts");
    593 	evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR,
    594 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full");
    595 	evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR,
    596 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure");
    597 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR,
    598 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc");
    599 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR,
    600 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc");
    601 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR,
    602 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc");
    603 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR,
    604 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc");
    605 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR,
    606 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc");
    607 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR,
    608 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc");
    609 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR,
    610 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc");
    611 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR,
    612 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc");
    613 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR,
    614 	    &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc");
    615 #endif
    616 
    617 	callout_init(&sc->sc_tick_ch, 0);
    618 	callout_init(&sc->sc_rx_watchdog, 0);
    619 	callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc);
    620 
    621 	sc->sc_att_stage = GEM_ATT_FINISHED;
    622 
    623 	return;
    624 }
    625 
    626 void
    627 gem_tick(void *arg)
    628 {
    629 	struct gem_softc *sc = arg;
    630 	int s;
    631 
    632 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) {
    633 		/*
    634 		 * We have to reset everything if we failed to get a
    635 		 * PCS interrupt.  Restarting the callout is handled
    636 		 * in gem_pcs_start().
    637 		 */
    638 		gem_init(&sc->sc_ethercom.ec_if);
    639 	} else {
    640 		s = splnet();
    641 		mii_tick(&sc->sc_mii);
    642 		splx(s);
    643 		callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
    644 	}
    645 }
    646 
    647 static int
    648 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set)
    649 {
    650 	int i;
    651 	u_int32_t reg;
    652 
    653 	for (i = TRIES; i--; DELAY(100)) {
    654 		reg = bus_space_read_4(sc->sc_bustag, h, r);
    655 		if ((reg & clr) == 0 && (reg & set) == set)
    656 			return (1);
    657 	}
    658 	return (0);
    659 }
    660 
    661 void
    662 gem_reset(struct gem_softc *sc)
    663 {
    664 	bus_space_tag_t t = sc->sc_bustag;
    665 	bus_space_handle_t h = sc->sc_h2;
    666 	int s;
    667 
    668 	s = splnet();
    669 	DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev)));
    670 	gem_reset_rx(sc);
    671 	gem_reset_tx(sc);
    672 
    673 	/* Do a full reset */
    674 	bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX);
    675 	if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
    676 		aprint_error_dev(sc->sc_dev, "cannot reset device\n");
    677 	splx(s);
    678 }
    679 
    680 
    681 /*
    682  * gem_rxdrain:
    683  *
    684  *	Drain the receive queue.
    685  */
    686 static void
    687 gem_rxdrain(struct gem_softc *sc)
    688 {
    689 	struct gem_rxsoft *rxs;
    690 	int i;
    691 
    692 	for (i = 0; i < GEM_NRXDESC; i++) {
    693 		rxs = &sc->sc_rxsoft[i];
    694 		if (rxs->rxs_mbuf != NULL) {
    695 			bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
    696 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
    697 			bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
    698 			m_freem(rxs->rxs_mbuf);
    699 			rxs->rxs_mbuf = NULL;
    700 		}
    701 	}
    702 }
    703 
    704 /*
    705  * Reset the whole thing.
    706  */
    707 static void
    708 gem_stop(struct ifnet *ifp, int disable)
    709 {
    710 	struct gem_softc *sc = ifp->if_softc;
    711 	struct gem_txsoft *txs;
    712 
    713 	DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev)));
    714 
    715 	callout_halt(&sc->sc_tick_ch, NULL);
    716 	callout_halt(&sc->sc_rx_watchdog, NULL);
    717 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
    718 		gem_pcs_stop(sc, disable);
    719 	else
    720 		mii_down(&sc->sc_mii);
    721 
    722 	/* XXX - Should we reset these instead? */
    723 	gem_disable_tx(sc);
    724 	gem_disable_rx(sc);
    725 
    726 	/*
    727 	 * Release any queued transmit buffers.
    728 	 */
    729 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
    730 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
    731 		if (txs->txs_mbuf != NULL) {
    732 			bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0,
    733 			    txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
    734 			bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap);
    735 			m_freem(txs->txs_mbuf);
    736 			txs->txs_mbuf = NULL;
    737 		}
    738 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
    739 	}
    740 
    741 	/*
    742 	 * Mark the interface down and cancel the watchdog timer.
    743 	 */
    744 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
    745 	sc->sc_if_flags = ifp->if_flags;
    746 	ifp->if_timer = 0;
    747 
    748 	if (disable)
    749 		gem_rxdrain(sc);
    750 }
    751 
    752 
    753 /*
    754  * Reset the receiver
    755  */
    756 int
    757 gem_reset_rx(struct gem_softc *sc)
    758 {
    759 	bus_space_tag_t t = sc->sc_bustag;
    760 	bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
    761 
    762 	/*
    763 	 * Resetting while DMA is in progress can cause a bus hang, so we
    764 	 * disable DMA first.
    765 	 */
    766 	gem_disable_rx(sc);
    767 	bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
    768 	bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    769 	/* Wait till it finishes */
    770 	if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0))
    771 		aprint_error_dev(sc->sc_dev, "cannot disable read dma\n");
    772 	/* Wait 5ms extra. */
    773 	delay(5000);
    774 
    775 	/* Finally, reset the ERX */
    776 	bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX);
    777 	bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
    778 	/* Wait till it finishes */
    779 	if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) {
    780 		aprint_error_dev(sc->sc_dev, "cannot reset receiver\n");
    781 		return (1);
    782 	}
    783 	return (0);
    784 }
    785 
    786 
    787 /*
    788  * Reset the receiver DMA engine.
    789  *
    790  * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW
    791  * etc in order to reset the receiver DMA engine only and not do a full
    792  * reset which amongst others also downs the link and clears the FIFOs.
    793  */
    794 static void
    795 gem_reset_rxdma(struct gem_softc *sc)
    796 {
    797 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    798 	bus_space_tag_t t = sc->sc_bustag;
    799 	bus_space_handle_t h = sc->sc_h1;
    800 	int i;
    801 
    802 	if (gem_reset_rx(sc) != 0) {
    803 		gem_init(ifp);
    804 		return;
    805 	}
    806 	for (i = 0; i < GEM_NRXDESC; i++)
    807 		if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
    808 			GEM_UPDATE_RXDESC(sc, i);
    809 	sc->sc_rxptr = 0;
    810 	GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
    811 	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
    812 
    813 	/* Reprogram Descriptor Ring Base Addresses */
    814 	/* NOTE: we use only 32-bit DMA addresses here. */
    815 	bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
    816 	bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
    817 
    818 	/* Redo ERX Configuration */
    819 	gem_rx_common(sc);
    820 
    821 	/* Give the reciever a swift kick */
    822 	bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4);
    823 }
    824 
    825 /*
    826  * Common RX configuration for gem_init() and gem_reset_rxdma().
    827  */
    828 static void
    829 gem_rx_common(struct gem_softc *sc)
    830 {
    831 	bus_space_tag_t t = sc->sc_bustag;
    832 	bus_space_handle_t h = sc->sc_h1;
    833 	u_int32_t v;
    834 
    835 	/* Encode Receive Descriptor ring size: four possible values */
    836 	v = gem_ringsize(GEM_NRXDESC /*XXX*/);
    837 
    838 	/* Set receive h/w checksum offset */
    839 #ifdef INET
    840 	v |= (ETHER_HDR_LEN + sizeof(struct ip) +
    841 	    ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
    842 	    ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT;
    843 #endif
    844 
    845 	/* Enable RX DMA */
    846 	bus_space_write_4(t, h, GEM_RX_CONFIG,
    847 	    v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
    848 	    (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN);
    849 
    850 	/*
    851 	 * The following value is for an OFF Threshold of about 3/4 full
    852 	 * and an ON Threshold of 1/4 full.
    853 	 */
    854 	bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
    855 	    (3 * sc->sc_rxfifosize / 256) |
    856 	    ((sc->sc_rxfifosize / 256) << 12));
    857 	bus_space_write_4(t, h, GEM_RX_BLANKING,
    858 	    (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8);
    859 }
    860 
    861 /*
    862  * Reset the transmitter
    863  */
    864 int
    865 gem_reset_tx(struct gem_softc *sc)
    866 {
    867 	bus_space_tag_t t = sc->sc_bustag;
    868 	bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
    869 
    870 	/*
    871 	 * Resetting while DMA is in progress can cause a bus hang, so we
    872 	 * disable DMA first.
    873 	 */
    874 	gem_disable_tx(sc);
    875 	bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
    876 	bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    877 	/* Wait till it finishes */
    878 	if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0))
    879 		aprint_error_dev(sc->sc_dev, "cannot disable read dma\n");
    880 	/* Wait 5ms extra. */
    881 	delay(5000);
    882 
    883 	/* Finally, reset the ETX */
    884 	bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX);
    885 	bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
    886 	/* Wait till it finishes */
    887 	if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) {
    888 		aprint_error_dev(sc->sc_dev, "cannot reset receiver\n");
    889 		return (1);
    890 	}
    891 	return (0);
    892 }
    893 
    894 /*
    895  * disable receiver.
    896  */
    897 int
    898 gem_disable_rx(struct gem_softc *sc)
    899 {
    900 	bus_space_tag_t t = sc->sc_bustag;
    901 	bus_space_handle_t h = sc->sc_h1;
    902 	u_int32_t cfg;
    903 
    904 	/* Flip the enable bit */
    905 	cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
    906 	cfg &= ~GEM_MAC_RX_ENABLE;
    907 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
    908 	bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    909 	/* Wait for it to finish */
    910 	return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
    911 }
    912 
    913 /*
    914  * disable transmitter.
    915  */
    916 int
    917 gem_disable_tx(struct gem_softc *sc)
    918 {
    919 	bus_space_tag_t t = sc->sc_bustag;
    920 	bus_space_handle_t h = sc->sc_h1;
    921 	u_int32_t cfg;
    922 
    923 	/* Flip the enable bit */
    924 	cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
    925 	cfg &= ~GEM_MAC_TX_ENABLE;
    926 	bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
    927 	bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    928 	/* Wait for it to finish */
    929 	return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
    930 }
    931 
    932 /*
    933  * Initialize interface.
    934  */
    935 int
    936 gem_meminit(struct gem_softc *sc)
    937 {
    938 	struct gem_rxsoft *rxs;
    939 	int i, error;
    940 
    941 	/*
    942 	 * Initialize the transmit descriptor ring.
    943 	 */
    944 	memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
    945 	for (i = 0; i < GEM_NTXDESC; i++) {
    946 		sc->sc_txdescs[i].gd_flags = 0;
    947 		sc->sc_txdescs[i].gd_addr = 0;
    948 	}
    949 	GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
    950 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
    951 	sc->sc_txfree = GEM_NTXDESC-1;
    952 	sc->sc_txnext = 0;
    953 	sc->sc_txwin = 0;
    954 
    955 	/*
    956 	 * Initialize the receive descriptor and receive job
    957 	 * descriptor rings.
    958 	 */
    959 	for (i = 0; i < GEM_NRXDESC; i++) {
    960 		rxs = &sc->sc_rxsoft[i];
    961 		if (rxs->rxs_mbuf == NULL) {
    962 			if ((error = gem_add_rxbuf(sc, i)) != 0) {
    963 				aprint_error_dev(sc->sc_dev,
    964 				    "unable to allocate or map rx "
    965 				    "buffer %d, error = %d\n",
    966 				    i, error);
    967 				/*
    968 				 * XXX Should attempt to run with fewer receive
    969 				 * XXX buffers instead of just failing.
    970 				 */
    971 				gem_rxdrain(sc);
    972 				return (1);
    973 			}
    974 		} else
    975 			GEM_INIT_RXDESC(sc, i);
    976 	}
    977 	sc->sc_rxptr = 0;
    978 	sc->sc_meminited = 1;
    979 	GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
    980 	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
    981 
    982 	return (0);
    983 }
    984 
    985 static int
    986 gem_ringsize(int sz)
    987 {
    988 	switch (sz) {
    989 	case 32:
    990 		return GEM_RING_SZ_32;
    991 	case 64:
    992 		return GEM_RING_SZ_64;
    993 	case 128:
    994 		return GEM_RING_SZ_128;
    995 	case 256:
    996 		return GEM_RING_SZ_256;
    997 	case 512:
    998 		return GEM_RING_SZ_512;
    999 	case 1024:
   1000 		return GEM_RING_SZ_1024;
   1001 	case 2048:
   1002 		return GEM_RING_SZ_2048;
   1003 	case 4096:
   1004 		return GEM_RING_SZ_4096;
   1005 	case 8192:
   1006 		return GEM_RING_SZ_8192;
   1007 	default:
   1008 		printf("gem: invalid Receive Descriptor ring size %d\n", sz);
   1009 		return GEM_RING_SZ_32;
   1010 	}
   1011 }
   1012 
   1013 
   1014 /*
   1015  * Start PCS
   1016  */
   1017 void
   1018 gem_pcs_start(struct gem_softc *sc)
   1019 {
   1020 	bus_space_tag_t t = sc->sc_bustag;
   1021 	bus_space_handle_t h = sc->sc_h1;
   1022 	uint32_t v;
   1023 
   1024 #ifdef GEM_DEBUG
   1025 	aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n");
   1026 #endif
   1027 
   1028 	/*
   1029 	 * Set up.  We must disable the MII before modifying the
   1030 	 * GEM_MII_ANAR register
   1031 	 */
   1032 	if (sc->sc_flags & GEM_SERDES) {
   1033 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
   1034 		    GEM_MII_DATAPATH_SERDES);
   1035 		bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
   1036 		    GEM_MII_SLINK_LOOPBACK);
   1037 	} else {
   1038 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
   1039 		    GEM_MII_DATAPATH_SERIAL);
   1040 		bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0);
   1041 	}
   1042 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
   1043 	v = bus_space_read_4(t, h, GEM_MII_ANAR);
   1044 	v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE);
   1045 	if (sc->sc_mii_media == IFM_AUTO)
   1046 		v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX);
   1047 	else if (sc->sc_mii_media == IFM_FDX) {
   1048 		v |= GEM_MII_ANEG_FUL_DUPLX;
   1049 		v &= ~GEM_MII_ANEG_HLF_DUPLX;
   1050 	} else if (sc->sc_mii_media == IFM_HDX) {
   1051 		v &= ~GEM_MII_ANEG_FUL_DUPLX;
   1052 		v |= GEM_MII_ANEG_HLF_DUPLX;
   1053 	}
   1054 
   1055 	/* Configure link. */
   1056 	bus_space_write_4(t, h, GEM_MII_ANAR, v);
   1057 	bus_space_write_4(t, h, GEM_MII_CONTROL,
   1058 	    GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN);
   1059 	bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
   1060 	gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT);
   1061 
   1062 	/* Start the 10 second timer */
   1063 	callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc);
   1064 }
   1065 
   1066 /*
   1067  * Stop PCS
   1068  */
   1069 void
   1070 gem_pcs_stop(struct gem_softc *sc, int disable)
   1071 {
   1072 	bus_space_tag_t t = sc->sc_bustag;
   1073 	bus_space_handle_t h = sc->sc_h1;
   1074 
   1075 #ifdef GEM_DEBUG
   1076 	aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n");
   1077 #endif
   1078 
   1079 	/* Tell link partner that we're going away */
   1080 	bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF);
   1081 
   1082 	/*
   1083 	 * Disable PCS MII.  The documentation suggests that setting
   1084 	 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto-
   1085 	 * negotiation will shut down the link.  However, it appears
   1086 	 * that we also need to unset the datapath mode.
   1087 	 */
   1088 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
   1089 	bus_space_write_4(t, h, GEM_MII_CONTROL,
   1090 	    GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN);
   1091 	bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII);
   1092 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
   1093 
   1094 	if (disable) {
   1095 		if (sc->sc_flags & GEM_SERDES)
   1096 			bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
   1097 				GEM_MII_SLINK_POWER_OFF);
   1098 		else
   1099 			bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
   1100 			    GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF);
   1101 	}
   1102 
   1103 	sc->sc_flags &= ~GEM_LINK;
   1104 	sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE;
   1105 	sc->sc_mii.mii_media_status = IFM_AVALID;
   1106 }
   1107 
   1108 
   1109 /*
   1110  * Initialization of interface; set up initialization block
   1111  * and transmit/receive descriptor rings.
   1112  */
   1113 int
   1114 gem_init(struct ifnet *ifp)
   1115 {
   1116 	struct gem_softc *sc = ifp->if_softc;
   1117 	bus_space_tag_t t = sc->sc_bustag;
   1118 	bus_space_handle_t h = sc->sc_h1;
   1119 	int rc = 0, s;
   1120 	u_int max_frame_size;
   1121 	u_int32_t v;
   1122 
   1123 	s = splnet();
   1124 
   1125 	DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev)));
   1126 	/*
   1127 	 * Initialization sequence. The numbered steps below correspond
   1128 	 * to the sequence outlined in section 6.3.5.1 in the Ethernet
   1129 	 * Channel Engine manual (part of the PCIO manual).
   1130 	 * See also the STP2002-STQ document from Sun Microsystems.
   1131 	 */
   1132 
   1133 	/* step 1 & 2. Reset the Ethernet Channel */
   1134 	gem_stop(ifp, 0);
   1135 	gem_reset(sc);
   1136 	DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev)));
   1137 
   1138 	/* Re-initialize the MIF */
   1139 	gem_mifinit(sc);
   1140 
   1141 	/* Set up correct datapath for non-SERDES/Serialink */
   1142 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 &&
   1143 	    sc->sc_variant != GEM_SUN_ERI)
   1144 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
   1145 		    GEM_MII_DATAPATH_MII);
   1146 
   1147 	/* Call MI reset function if any */
   1148 	if (sc->sc_hwreset)
   1149 		(*sc->sc_hwreset)(sc);
   1150 
   1151 	/* step 3. Setup data structures in host memory */
   1152 	if (gem_meminit(sc) != 0)
   1153 		return 1;
   1154 
   1155 	/* step 4. TX MAC registers & counters */
   1156 	gem_init_regs(sc);
   1157 	max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU);
   1158 	max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN;
   1159 	if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
   1160 		max_frame_size += ETHER_VLAN_ENCAP_LEN;
   1161 	bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
   1162 	    max_frame_size|/* burst size */(0x2000<<16));
   1163 
   1164 	/* step 5. RX MAC registers & counters */
   1165 	gem_setladrf(sc);
   1166 
   1167 	/* step 6 & 7. Program Descriptor Ring Base Addresses */
   1168 	/* NOTE: we use only 32-bit DMA addresses here. */
   1169 	bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
   1170 	bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
   1171 
   1172 	bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
   1173 	bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
   1174 
   1175 	/* step 8. Global Configuration & Interrupt Mask */
   1176 	gem_inten(sc);
   1177 	bus_space_write_4(t, h, GEM_MAC_RX_MASK,
   1178 			GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
   1179 	bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */
   1180 	bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK,
   1181 	    GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
   1182 
   1183 	/* step 9. ETX Configuration: use mostly default values */
   1184 
   1185 	/* Enable TX DMA */
   1186 	v = gem_ringsize(GEM_NTXDESC /*XXX*/);
   1187 	bus_space_write_4(t, h, GEM_TX_CONFIG,
   1188 	    v | GEM_TX_CONFIG_TXDMA_EN |
   1189 	    (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) &
   1190 	    GEM_TX_CONFIG_TXFIFO_TH));
   1191 	bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext);
   1192 
   1193 	/* step 10. ERX Configuration */
   1194 	gem_rx_common(sc);
   1195 
   1196 	/* step 11. Configure Media */
   1197 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 &&
   1198 	    (rc = mii_ifmedia_change(&sc->sc_mii)) != 0)
   1199 		goto out;
   1200 
   1201 	/* step 12. RX_MAC Configuration Register */
   1202 	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
   1203 	v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC;
   1204 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
   1205 
   1206 	/* step 14. Issue Transmit Pending command */
   1207 
   1208 	/* Call MI initialization function if any */
   1209 	if (sc->sc_hwinit)
   1210 		(*sc->sc_hwinit)(sc);
   1211 
   1212 
   1213 	/* step 15.  Give the reciever a swift kick */
   1214 	bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
   1215 
   1216 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
   1217 		/* Configure PCS */
   1218 		gem_pcs_start(sc);
   1219 	else
   1220 		/* Start the one second timer. */
   1221 		callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
   1222 
   1223 	sc->sc_flags &= ~GEM_LINK;
   1224 	ifp->if_flags |= IFF_RUNNING;
   1225 	ifp->if_flags &= ~IFF_OACTIVE;
   1226 	ifp->if_timer = 0;
   1227 	sc->sc_if_flags = ifp->if_flags;
   1228 out:
   1229 	splx(s);
   1230 
   1231 	return (0);
   1232 }
   1233 
   1234 void
   1235 gem_init_regs(struct gem_softc *sc)
   1236 {
   1237 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1238 	bus_space_tag_t t = sc->sc_bustag;
   1239 	bus_space_handle_t h = sc->sc_h1;
   1240 	const u_char *laddr = CLLADDR(ifp->if_sadl);
   1241 	u_int32_t v;
   1242 
   1243 	/* These regs are not cleared on reset */
   1244 	if (!sc->sc_inited) {
   1245 
   1246 		/* Load recommended values */
   1247 		bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00);
   1248 		bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08);
   1249 		bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04);
   1250 
   1251 		bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
   1252 		/* Max frame and max burst size */
   1253 		bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
   1254 		    ETHER_MAX_LEN | (0x2000<<16));
   1255 
   1256 		bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07);
   1257 		bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04);
   1258 		bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
   1259 		bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
   1260 		bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
   1261 		    ((laddr[5]<<8)|laddr[4])&0x3ff);
   1262 
   1263 		/* Secondary MAC addr set to 0:0:0:0:0:0 */
   1264 		bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
   1265 		bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
   1266 		bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
   1267 
   1268 		/* MAC control addr set to 01:80:c2:00:00:01 */
   1269 		bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
   1270 		bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
   1271 		bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
   1272 
   1273 		/* MAC filter addr set to 0:0:0:0:0:0 */
   1274 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
   1275 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
   1276 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
   1277 
   1278 		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
   1279 		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
   1280 
   1281 		sc->sc_inited = 1;
   1282 	}
   1283 
   1284 	/* Counters need to be zeroed */
   1285 	bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
   1286 	bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
   1287 	bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
   1288 	bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
   1289 	bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
   1290 	bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
   1291 	bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
   1292 	bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
   1293 	bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
   1294 	bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
   1295 	bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
   1296 
   1297 	/* Set XOFF PAUSE time. */
   1298 	bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
   1299 
   1300 	/*
   1301 	 * Set the internal arbitration to "infinite" bursts of the
   1302 	 * maximum length of 31 * 64 bytes so DMA transfers aren't
   1303 	 * split up in cache line size chunks. This greatly improves
   1304 	 * especially RX performance.
   1305 	 * Enable silicon bug workarounds for the Apple variants.
   1306 	 */
   1307 	bus_space_write_4(t, h, GEM_CONFIG,
   1308 	    GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
   1309 	    ((sc->sc_flags & GEM_PCI) ?
   1310 	    GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ?
   1311 	    GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
   1312 
   1313 	/*
   1314 	 * Set the station address.
   1315 	 */
   1316 	bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
   1317 	bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
   1318 	bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
   1319 
   1320 	/*
   1321 	 * Enable MII outputs.  Enable GMII if there is a gigabit PHY.
   1322 	 */
   1323 	sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
   1324 	v = GEM_MAC_XIF_TX_MII_ENA;
   1325 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0)  {
   1326 		if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
   1327 			v |= GEM_MAC_XIF_FDPLX_LED;
   1328 				if (sc->sc_flags & GEM_GIGABIT)
   1329 					v |= GEM_MAC_XIF_GMII_MODE;
   1330 		}
   1331 	} else {
   1332 		v |= GEM_MAC_XIF_GMII_MODE;
   1333 	}
   1334 	bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
   1335 }
   1336 
   1337 #ifdef GEM_DEBUG
   1338 static void
   1339 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc)
   1340 {
   1341 	int i;
   1342 
   1343 	for (i = firstdesc;; i = GEM_NEXTTX(i)) {
   1344 		printf("descriptor %d:\t", i);
   1345 		printf("gd_flags:   0x%016" PRIx64 "\t",
   1346 			GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
   1347 		printf("gd_addr: 0x%016" PRIx64 "\n",
   1348 			GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
   1349 		if (i == lastdesc)
   1350 			break;
   1351 	}
   1352 }
   1353 #endif
   1354 
   1355 static void
   1356 gem_start(struct ifnet *ifp)
   1357 {
   1358 	struct gem_softc *sc = ifp->if_softc;
   1359 	struct mbuf *m0, *m;
   1360 	struct gem_txsoft *txs;
   1361 	bus_dmamap_t dmamap;
   1362 	int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg;
   1363 	uint64_t flags = 0;
   1364 
   1365 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
   1366 		return;
   1367 
   1368 	/*
   1369 	 * Remember the previous number of free descriptors and
   1370 	 * the first descriptor we'll use.
   1371 	 */
   1372 	ofree = sc->sc_txfree;
   1373 	firsttx = sc->sc_txnext;
   1374 
   1375 	DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n",
   1376 	    device_xname(sc->sc_dev), ofree, firsttx));
   1377 
   1378 	/*
   1379 	 * Loop through the send queue, setting up transmit descriptors
   1380 	 * until we drain the queue, or use up all available transmit
   1381 	 * descriptors.
   1382 	 */
   1383 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL &&
   1384 	    sc->sc_txfree != 0) {
   1385 		/*
   1386 		 * Grab a packet off the queue.
   1387 		 */
   1388 		IFQ_POLL(&ifp->if_snd, m0);
   1389 		if (m0 == NULL)
   1390 			break;
   1391 		m = NULL;
   1392 
   1393 		dmamap = txs->txs_dmamap;
   1394 
   1395 		/*
   1396 		 * Load the DMA map.  If this fails, the packet either
   1397 		 * didn't fit in the alloted number of segments, or we were
   1398 		 * short on resources.  In this case, we'll copy and try
   1399 		 * again.
   1400 		 */
   1401 		if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0,
   1402 		      BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 ||
   1403 		      (m0->m_pkthdr.len < ETHER_MIN_TX &&
   1404 		       dmamap->dm_nsegs == GEM_NTXSEGS)) {
   1405 			if (m0->m_pkthdr.len > MCLBYTES) {
   1406 				aprint_error_dev(sc->sc_dev,
   1407 				    "unable to allocate jumbo Tx cluster\n");
   1408 				IFQ_DEQUEUE(&ifp->if_snd, m0);
   1409 				m_freem(m0);
   1410 				continue;
   1411 			}
   1412 			MGETHDR(m, M_DONTWAIT, MT_DATA);
   1413 			if (m == NULL) {
   1414 				aprint_error_dev(sc->sc_dev,
   1415 				    "unable to allocate Tx mbuf\n");
   1416 				break;
   1417 			}
   1418 			MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner);
   1419 			if (m0->m_pkthdr.len > MHLEN) {
   1420 				MCLGET(m, M_DONTWAIT);
   1421 				if ((m->m_flags & M_EXT) == 0) {
   1422 					aprint_error_dev(sc->sc_dev,
   1423 					    "unable to allocate Tx cluster\n");
   1424 					m_freem(m);
   1425 					break;
   1426 				}
   1427 			}
   1428 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
   1429 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
   1430 			error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap,
   1431 			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
   1432 			if (error) {
   1433 				aprint_error_dev(sc->sc_dev,
   1434 				    "unable to load Tx buffer, error = %d\n",
   1435 				    error);
   1436 				break;
   1437 			}
   1438 		}
   1439 
   1440 		/*
   1441 		 * Ensure we have enough descriptors free to describe
   1442 		 * the packet.
   1443 		 */
   1444 		if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ?
   1445 		     (sc->sc_txfree - 1) : sc->sc_txfree)) {
   1446 			/*
   1447 			 * Not enough free descriptors to transmit this
   1448 			 * packet.  We haven't committed to anything yet,
   1449 			 * so just unload the DMA map, put the packet
   1450 			 * back on the queue, and punt.  Notify the upper
   1451 			 * layer that there are no more slots left.
   1452 			 *
   1453 			 * XXX We could allocate an mbuf and copy, but
   1454 			 * XXX it is worth it?
   1455 			 */
   1456 			ifp->if_flags |= IFF_OACTIVE;
   1457 			sc->sc_if_flags = ifp->if_flags;
   1458 			bus_dmamap_unload(sc->sc_dmatag, dmamap);
   1459 			if (m != NULL)
   1460 				m_freem(m);
   1461 			break;
   1462 		}
   1463 
   1464 		IFQ_DEQUEUE(&ifp->if_snd, m0);
   1465 		if (m != NULL) {
   1466 			m_freem(m0);
   1467 			m0 = m;
   1468 		}
   1469 
   1470 		/*
   1471 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
   1472 		 */
   1473 
   1474 		/* Sync the DMA map. */
   1475 		bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize,
   1476 		    BUS_DMASYNC_PREWRITE);
   1477 
   1478 		/*
   1479 		 * Initialize the transmit descriptors.
   1480 		 */
   1481 		for (nexttx = sc->sc_txnext, seg = 0;
   1482 		     seg < dmamap->dm_nsegs;
   1483 		     seg++, nexttx = GEM_NEXTTX(nexttx)) {
   1484 
   1485 			/*
   1486 			 * If this is the first descriptor we're
   1487 			 * enqueueing, set the start of packet flag,
   1488 			 * and the checksum stuff if we want the hardware
   1489 			 * to do it.
   1490 			 */
   1491 			sc->sc_txdescs[nexttx].gd_addr =
   1492 			    GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr);
   1493 			flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE;
   1494 			if (nexttx == firsttx) {
   1495 				flags |= GEM_TD_START_OF_PACKET;
   1496 				if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
   1497 					sc->sc_txwin = 0;
   1498 					flags |= GEM_TD_INTERRUPT_ME;
   1499 				}
   1500 
   1501 #ifdef INET
   1502 				/* h/w checksum */
   1503 				if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 &&
   1504 				    m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
   1505 					struct ether_header *eh;
   1506 					uint16_t offset, start;
   1507 
   1508 					eh = mtod(m0, struct ether_header *);
   1509 					switch (ntohs(eh->ether_type)) {
   1510 					case ETHERTYPE_IP:
   1511 						start = ETHER_HDR_LEN;
   1512 						break;
   1513 					case ETHERTYPE_VLAN:
   1514 						start = ETHER_HDR_LEN +
   1515 							ETHER_VLAN_ENCAP_LEN;
   1516 						break;
   1517 					default:
   1518 						/* unsupported, drop it */
   1519 						m_free(m0);
   1520 						continue;
   1521 					}
   1522 					start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   1523 					offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start;
   1524 					flags |= (start <<
   1525 						  GEM_TD_CXSUM_STARTSHFT) |
   1526 						 (offset <<
   1527 						  GEM_TD_CXSUM_STUFFSHFT) |
   1528 						 GEM_TD_CXSUM_ENABLE;
   1529 				}
   1530 #endif
   1531 			}
   1532 			if (seg == dmamap->dm_nsegs - 1) {
   1533 				flags |= GEM_TD_END_OF_PACKET;
   1534 			} else {
   1535 				/* last flag set outside of loop */
   1536 				sc->sc_txdescs[nexttx].gd_flags =
   1537 					GEM_DMA_WRITE(sc, flags);
   1538 			}
   1539 			lasttx = nexttx;
   1540 		}
   1541 		if (m0->m_pkthdr.len < ETHER_MIN_TX) {
   1542 			/* add padding buffer at end of chain */
   1543 			flags &= ~GEM_TD_END_OF_PACKET;
   1544 			sc->sc_txdescs[lasttx].gd_flags =
   1545 			    GEM_DMA_WRITE(sc, flags);
   1546 
   1547 			sc->sc_txdescs[nexttx].gd_addr =
   1548 			    GEM_DMA_WRITE(sc,
   1549 			    sc->sc_nulldmamap->dm_segs[0].ds_addr);
   1550 			flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) &
   1551 			    GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET;
   1552 			lasttx = nexttx;
   1553 			nexttx = GEM_NEXTTX(nexttx);
   1554 			seg++;
   1555 		}
   1556 		sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags);
   1557 
   1558 		KASSERT(lasttx != -1);
   1559 
   1560 		/*
   1561 		 * Store a pointer to the packet so we can free it later,
   1562 		 * and remember what txdirty will be once the packet is
   1563 		 * done.
   1564 		 */
   1565 		txs->txs_mbuf = m0;
   1566 		txs->txs_firstdesc = sc->sc_txnext;
   1567 		txs->txs_lastdesc = lasttx;
   1568 		txs->txs_ndescs = seg;
   1569 
   1570 #ifdef GEM_DEBUG
   1571 		if (ifp->if_flags & IFF_DEBUG) {
   1572 			printf("     gem_start %p transmit chain:\n", txs);
   1573 			gem_txsoft_print(sc, txs->txs_firstdesc,
   1574 			    txs->txs_lastdesc);
   1575 		}
   1576 #endif
   1577 
   1578 		/* Sync the descriptors we're using. */
   1579 		GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs,
   1580 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1581 
   1582 		/* Advance the tx pointer. */
   1583 		sc->sc_txfree -= txs->txs_ndescs;
   1584 		sc->sc_txnext = nexttx;
   1585 
   1586 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
   1587 		SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
   1588 
   1589 		/*
   1590 		 * Pass the packet to any BPF listeners.
   1591 		 */
   1592 		bpf_mtap(ifp, m0);
   1593 	}
   1594 
   1595 	if (txs == NULL || sc->sc_txfree == 0) {
   1596 		/* No more slots left; notify upper layer. */
   1597 		ifp->if_flags |= IFF_OACTIVE;
   1598 		sc->sc_if_flags = ifp->if_flags;
   1599 	}
   1600 
   1601 	if (sc->sc_txfree != ofree) {
   1602 		DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n",
   1603 		    device_xname(sc->sc_dev), lasttx, firsttx));
   1604 		/*
   1605 		 * The entire packet chain is set up.
   1606 		 * Kick the transmitter.
   1607 		 */
   1608 		DPRINTF(sc, ("%s: gem_start: kicking tx %d\n",
   1609 			device_xname(sc->sc_dev), nexttx));
   1610 		bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK,
   1611 			sc->sc_txnext);
   1612 
   1613 		/* Set a watchdog timer in case the chip flakes out. */
   1614 		ifp->if_timer = 5;
   1615 		DPRINTF(sc, ("%s: gem_start: watchdog %d\n",
   1616 			device_xname(sc->sc_dev), ifp->if_timer));
   1617 	}
   1618 }
   1619 
   1620 /*
   1621  * Transmit interrupt.
   1622  */
   1623 int
   1624 gem_tint(struct gem_softc *sc)
   1625 {
   1626 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1627 	bus_space_tag_t t = sc->sc_bustag;
   1628 	bus_space_handle_t mac = sc->sc_h1;
   1629 	struct gem_txsoft *txs;
   1630 	int txlast;
   1631 	int progress = 0;
   1632 	u_int32_t v;
   1633 
   1634 	DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev)));
   1635 
   1636 	/* Unload collision counters ... */
   1637 	v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
   1638 	    bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
   1639 	ifp->if_collisions += v +
   1640 	    bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
   1641 	    bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT);
   1642 	ifp->if_oerrors += v;
   1643 
   1644 	/* ... then clear the hardware counters. */
   1645 	bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
   1646 	bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
   1647 	bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
   1648 	bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
   1649 
   1650 	/*
   1651 	 * Go through our Tx list and free mbufs for those
   1652 	 * frames that have been transmitted.
   1653 	 */
   1654 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
   1655 		/*
   1656 		 * In theory, we could harvest some descriptors before
   1657 		 * the ring is empty, but that's a bit complicated.
   1658 		 *
   1659 		 * GEM_TX_COMPLETION points to the last descriptor
   1660 		 * processed +1.
   1661 		 *
   1662 		 * Let's assume that the NIC writes back to the Tx
   1663 		 * descriptors before it updates the completion
   1664 		 * register.  If the NIC has posted writes to the
   1665 		 * Tx descriptors, PCI ordering requires that the
   1666 		 * posted writes flush to RAM before the register-read
   1667 		 * finishes.  So let's read the completion register,
   1668 		 * before syncing the descriptors, so that we
   1669 		 * examine Tx descriptors that are at least as
   1670 		 * current as the completion register.
   1671 		 */
   1672 		txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
   1673 		DPRINTF(sc,
   1674 			("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n",
   1675 				txs->txs_lastdesc, txlast));
   1676 		if (txs->txs_firstdesc <= txs->txs_lastdesc) {
   1677 			if (txlast >= txs->txs_firstdesc &&
   1678 			    txlast <= txs->txs_lastdesc)
   1679 				break;
   1680 		} else if (txlast >= txs->txs_firstdesc ||
   1681 			   txlast <= txs->txs_lastdesc)
   1682 			break;
   1683 
   1684 		GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs,
   1685 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1686 
   1687 #ifdef GEM_DEBUG	/* XXX DMA synchronization? */
   1688 		if (ifp->if_flags & IFF_DEBUG) {
   1689 			printf("    txsoft %p transmit chain:\n", txs);
   1690 			gem_txsoft_print(sc, txs->txs_firstdesc,
   1691 			    txs->txs_lastdesc);
   1692 		}
   1693 #endif
   1694 
   1695 
   1696 		DPRINTF(sc, ("gem_tint: releasing a desc\n"));
   1697 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
   1698 
   1699 		sc->sc_txfree += txs->txs_ndescs;
   1700 
   1701 		bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap,
   1702 		    0, txs->txs_dmamap->dm_mapsize,
   1703 		    BUS_DMASYNC_POSTWRITE);
   1704 		bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap);
   1705 		if (txs->txs_mbuf != NULL) {
   1706 			m_freem(txs->txs_mbuf);
   1707 			txs->txs_mbuf = NULL;
   1708 		}
   1709 
   1710 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
   1711 
   1712 		ifp->if_opackets++;
   1713 		progress = 1;
   1714 	}
   1715 
   1716 #if 0
   1717 	DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x "
   1718 		"GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n",
   1719 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE),
   1720 		((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1,
   1721 			GEM_TX_DATA_PTR_HI) << 32) |
   1722 			     bus_space_read_4(sc->sc_bustag, sc->sc_h1,
   1723 			GEM_TX_DATA_PTR_LO),
   1724 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION)));
   1725 #endif
   1726 
   1727 	if (progress) {
   1728 		if (sc->sc_txfree == GEM_NTXDESC - 1)
   1729 			sc->sc_txwin = 0;
   1730 
   1731 		/* Freed some descriptors, so reset IFF_OACTIVE and restart. */
   1732 		ifp->if_flags &= ~IFF_OACTIVE;
   1733 		sc->sc_if_flags = ifp->if_flags;
   1734 		ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
   1735 		gem_start(ifp);
   1736 	}
   1737 	DPRINTF(sc, ("%s: gem_tint: watchdog %d\n",
   1738 		device_xname(sc->sc_dev), ifp->if_timer));
   1739 
   1740 	return (1);
   1741 }
   1742 
   1743 /*
   1744  * Receive interrupt.
   1745  */
   1746 int
   1747 gem_rint(struct gem_softc *sc)
   1748 {
   1749 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1750 	bus_space_tag_t t = sc->sc_bustag;
   1751 	bus_space_handle_t h = sc->sc_h1;
   1752 	struct gem_rxsoft *rxs;
   1753 	struct mbuf *m;
   1754 	u_int64_t rxstat;
   1755 	u_int32_t rxcomp;
   1756 	int i, len, progress = 0;
   1757 
   1758 	DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev)));
   1759 
   1760 	/*
   1761 	 * Ignore spurious interrupt that sometimes occurs before
   1762 	 * we are set up when we network boot.
   1763 	 */
   1764 	if (!sc->sc_meminited)
   1765 		return 1;
   1766 
   1767 	/*
   1768 	 * Read the completion register once.  This limits
   1769 	 * how long the following loop can execute.
   1770 	 */
   1771 	rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
   1772 
   1773 	/*
   1774 	 * XXX Read the lastrx only once at the top for speed.
   1775 	 */
   1776 	DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n",
   1777 		sc->sc_rxptr, rxcomp));
   1778 
   1779 	/*
   1780 	 * Go into the loop at least once.
   1781 	 */
   1782 	for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp;
   1783 	     i = GEM_NEXTRX(i)) {
   1784 		rxs = &sc->sc_rxsoft[i];
   1785 
   1786 		GEM_CDRXSYNC(sc, i,
   1787 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1788 
   1789 		rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
   1790 
   1791 		if (rxstat & GEM_RD_OWN) {
   1792 			GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
   1793 			/*
   1794 			 * We have processed all of the receive buffers.
   1795 			 */
   1796 			break;
   1797 		}
   1798 
   1799 		progress++;
   1800 		ifp->if_ipackets++;
   1801 
   1802 		if (rxstat & GEM_RD_BAD_CRC) {
   1803 			ifp->if_ierrors++;
   1804 			aprint_error_dev(sc->sc_dev,
   1805 			    "receive error: CRC error\n");
   1806 			GEM_INIT_RXDESC(sc, i);
   1807 			continue;
   1808 		}
   1809 
   1810 		bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
   1811 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   1812 #ifdef GEM_DEBUG
   1813 		if (ifp->if_flags & IFF_DEBUG) {
   1814 			printf("    rxsoft %p descriptor %d: ", rxs, i);
   1815 			printf("gd_flags: 0x%016llx\t", (long long)
   1816 				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
   1817 			printf("gd_addr: 0x%016llx\n", (long long)
   1818 				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
   1819 		}
   1820 #endif
   1821 
   1822 		/* No errors; receive the packet. */
   1823 		len = GEM_RD_BUFLEN(rxstat);
   1824 
   1825 		/*
   1826 		 * Allocate a new mbuf cluster.  If that fails, we are
   1827 		 * out of memory, and must drop the packet and recycle
   1828 		 * the buffer that's already attached to this descriptor.
   1829 		 */
   1830 		m = rxs->rxs_mbuf;
   1831 		if (gem_add_rxbuf(sc, i) != 0) {
   1832 			GEM_COUNTER_INCR(sc, sc_ev_rxnobuf);
   1833 			ifp->if_ierrors++;
   1834 			aprint_error_dev(sc->sc_dev,
   1835 			    "receive error: RX no buffer space\n");
   1836 			GEM_INIT_RXDESC(sc, i);
   1837 			bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
   1838 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   1839 			continue;
   1840 		}
   1841 		m->m_data += 2; /* We're already off by two */
   1842 
   1843 		m->m_pkthdr.rcvif = ifp;
   1844 		m->m_pkthdr.len = m->m_len = len;
   1845 
   1846 		/*
   1847 		 * Pass this up to any BPF listeners, but only
   1848 		 * pass it up the stack if it's for us.
   1849 		 */
   1850 		bpf_mtap(ifp, m);
   1851 
   1852 #ifdef INET
   1853 		/* hardware checksum */
   1854 		if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) {
   1855 			struct ether_header *eh;
   1856 			struct ip *ip;
   1857 			int32_t hlen, pktlen;
   1858 
   1859 			if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) {
   1860 				pktlen = m->m_pkthdr.len - ETHER_HDR_LEN -
   1861 					 ETHER_VLAN_ENCAP_LEN;
   1862 				eh = (struct ether_header *) (mtod(m, char *) +
   1863 					ETHER_VLAN_ENCAP_LEN);
   1864 			} else {
   1865 				pktlen = m->m_pkthdr.len - ETHER_HDR_LEN;
   1866 				eh = mtod(m, struct ether_header *);
   1867 			}
   1868 			if (ntohs(eh->ether_type) != ETHERTYPE_IP)
   1869 				goto swcsum;
   1870 			ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN);
   1871 
   1872 			/* IPv4 only */
   1873 			if (ip->ip_v != IPVERSION)
   1874 				goto swcsum;
   1875 
   1876 			hlen = ip->ip_hl << 2;
   1877 			if (hlen < sizeof(struct ip))
   1878 				goto swcsum;
   1879 
   1880 			/*
   1881 			 * bail if too short, has random trailing garbage,
   1882 			 * truncated, fragment, or has ethernet pad.
   1883 			 */
   1884 			if ((ntohs(ip->ip_len) < hlen) ||
   1885 			    (ntohs(ip->ip_len) != pktlen) ||
   1886 			    (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)))
   1887 				goto swcsum;
   1888 
   1889 			switch (ip->ip_p) {
   1890 			case IPPROTO_TCP:
   1891 				if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4))
   1892 					goto swcsum;
   1893 				if (pktlen < (hlen + sizeof(struct tcphdr)))
   1894 					goto swcsum;
   1895 				m->m_pkthdr.csum_flags = M_CSUM_TCPv4;
   1896 				break;
   1897 			case IPPROTO_UDP:
   1898 				/* FALLTHROUGH */
   1899 			default:
   1900 				goto swcsum;
   1901 			}
   1902 
   1903 			/* the uncomplemented sum is expected */
   1904 			m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM;
   1905 
   1906 			/* if the pkt had ip options, we have to deduct them */
   1907 			if (hlen > sizeof(struct ip)) {
   1908 				uint16_t *opts;
   1909 				uint32_t optsum, temp;
   1910 
   1911 				optsum = 0;
   1912 				temp = hlen - sizeof(struct ip);
   1913 				opts = (uint16_t *) ((char *) ip +
   1914 					sizeof(struct ip));
   1915 
   1916 				while (temp > 1) {
   1917 					optsum += ntohs(*opts++);
   1918 					temp -= 2;
   1919 				}
   1920 				while (optsum >> 16)
   1921 					optsum = (optsum >> 16) +
   1922 						 (optsum & 0xffff);
   1923 
   1924 				/* Deduct ip opts sum from hwsum. */
   1925 				m->m_pkthdr.csum_data += (uint16_t)~optsum;
   1926 
   1927 				while (m->m_pkthdr.csum_data >> 16)
   1928 					m->m_pkthdr.csum_data =
   1929 						(m->m_pkthdr.csum_data >> 16) +
   1930 						(m->m_pkthdr.csum_data &
   1931 						 0xffff);
   1932 			}
   1933 
   1934 			m->m_pkthdr.csum_flags |= M_CSUM_DATA |
   1935 						  M_CSUM_NO_PSEUDOHDR;
   1936 		} else
   1937 swcsum:
   1938 			m->m_pkthdr.csum_flags = 0;
   1939 #endif
   1940 		/* Pass it on. */
   1941 		(*ifp->if_input)(ifp, m);
   1942 	}
   1943 
   1944 	if (progress) {
   1945 		/* Update the receive pointer. */
   1946 		if (i == sc->sc_rxptr) {
   1947 			GEM_COUNTER_INCR(sc, sc_ev_rxfull);
   1948 #ifdef GEM_DEBUG
   1949 			if (ifp->if_flags & IFF_DEBUG)
   1950 				printf("%s: rint: ring wrap\n",
   1951 				    device_xname(sc->sc_dev));
   1952 #endif
   1953 		}
   1954 		sc->sc_rxptr = i;
   1955 		bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
   1956 	}
   1957 #ifdef GEM_COUNTERS
   1958 	if (progress <= 4) {
   1959 		GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]);
   1960 	} else if (progress < 32) {
   1961 		if (progress < 16)
   1962 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]);
   1963 		else
   1964 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]);
   1965 
   1966 	} else {
   1967 		if (progress < 64)
   1968 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]);
   1969 		else
   1970 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]);
   1971 	}
   1972 #endif
   1973 
   1974 	DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n",
   1975 		sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
   1976 
   1977 	/* Read error counters ... */
   1978 	ifp->if_ierrors +=
   1979 	    bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) +
   1980 	    bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) +
   1981 	    bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) +
   1982 	    bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL);
   1983 
   1984 	/* ... then clear the hardware counters. */
   1985 	bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
   1986 	bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
   1987 	bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
   1988 	bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
   1989 
   1990 	return (1);
   1991 }
   1992 
   1993 
   1994 /*
   1995  * gem_add_rxbuf:
   1996  *
   1997  *	Add a receive buffer to the indicated descriptor.
   1998  */
   1999 int
   2000 gem_add_rxbuf(struct gem_softc *sc, int idx)
   2001 {
   2002 	struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
   2003 	struct mbuf *m;
   2004 	int error;
   2005 
   2006 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   2007 	if (m == NULL)
   2008 		return (ENOBUFS);
   2009 
   2010 	MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
   2011 	MCLGET(m, M_DONTWAIT);
   2012 	if ((m->m_flags & M_EXT) == 0) {
   2013 		m_freem(m);
   2014 		return (ENOBUFS);
   2015 	}
   2016 
   2017 #ifdef GEM_DEBUG
   2018 /* bzero the packet to check DMA */
   2019 	memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
   2020 #endif
   2021 
   2022 	if (rxs->rxs_mbuf != NULL)
   2023 		bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
   2024 
   2025 	rxs->rxs_mbuf = m;
   2026 
   2027 	error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap,
   2028 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
   2029 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
   2030 	if (error) {
   2031 		aprint_error_dev(sc->sc_dev,
   2032 		    "can't load rx DMA map %d, error = %d\n", idx, error);
   2033 		panic("gem_add_rxbuf");	/* XXX */
   2034 	}
   2035 
   2036 	bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
   2037 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   2038 
   2039 	GEM_INIT_RXDESC(sc, idx);
   2040 
   2041 	return (0);
   2042 }
   2043 
   2044 
   2045 int
   2046 gem_eint(struct gem_softc *sc, u_int status)
   2047 {
   2048 	char bits[128];
   2049 	u_int32_t r, v;
   2050 
   2051 	if ((status & GEM_INTR_MIF) != 0) {
   2052 		printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev));
   2053 		return (1);
   2054 	}
   2055 
   2056 	if ((status & GEM_INTR_RX_TAG_ERR) != 0) {
   2057 		gem_reset_rxdma(sc);
   2058 		return (1);
   2059 	}
   2060 
   2061 	if (status & GEM_INTR_BERR) {
   2062 		if (sc->sc_flags & GEM_PCI)
   2063 			r = GEM_ERROR_STATUS;
   2064 		else
   2065 			r = GEM_SBUS_ERROR_STATUS;
   2066 		bus_space_read_4(sc->sc_bustag, sc->sc_h2, r);
   2067 		v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r);
   2068 		aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n",
   2069 		    v);
   2070 		return (1);
   2071 	}
   2072 	snprintb(bits, sizeof(bits), GEM_INTR_BITS, status);
   2073 	printf("%s: status=%s\n", device_xname(sc->sc_dev), bits);
   2074 
   2075 	return (1);
   2076 }
   2077 
   2078 
   2079 /*
   2080  * PCS interrupts.
   2081  * We should receive these when the link status changes, but sometimes
   2082  * we don't receive them for link up.  We compensate for this in the
   2083  * gem_tick() callout.
   2084  */
   2085 int
   2086 gem_pint(struct gem_softc *sc)
   2087 {
   2088 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2089 	bus_space_tag_t t = sc->sc_bustag;
   2090 	bus_space_handle_t h = sc->sc_h1;
   2091 	u_int32_t v, v2;
   2092 
   2093 	/*
   2094 	 * Clear the PCS interrupt from GEM_STATUS.  The PCS register is
   2095 	 * latched, so we have to read it twice.  There is only one bit in
   2096 	 * use, so the value is meaningless.
   2097 	 */
   2098 	bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS);
   2099 	bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS);
   2100 
   2101 	if ((ifp->if_flags & IFF_UP) == 0)
   2102 		return 1;
   2103 
   2104 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0)
   2105 		return 1;
   2106 
   2107 	v = bus_space_read_4(t, h, GEM_MII_STATUS);
   2108 	/* If we see remote fault, our link partner is probably going away */
   2109 	if ((v & GEM_MII_STATUS_REM_FLT) != 0) {
   2110 		gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0);
   2111 		v = bus_space_read_4(t, h, GEM_MII_STATUS);
   2112 	/* Otherwise, we may need to wait after auto-negotiation completes */
   2113 	} else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) ==
   2114 	    GEM_MII_STATUS_ANEG_CPT) {
   2115 		gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS);
   2116 		v = bus_space_read_4(t, h, GEM_MII_STATUS);
   2117 	}
   2118 	if ((v & GEM_MII_STATUS_LINK_STS) != 0) {
   2119 		if (sc->sc_flags & GEM_LINK) {
   2120 			return 1;
   2121 		}
   2122 		callout_stop(&sc->sc_tick_ch);
   2123 		v = bus_space_read_4(t, h, GEM_MII_ANAR);
   2124 		v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR);
   2125 		sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX;
   2126 		sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE;
   2127 		v &= v2;
   2128 		if (v & GEM_MII_ANEG_FUL_DUPLX) {
   2129 			sc->sc_mii.mii_media_active |= IFM_FDX;
   2130 #ifdef GEM_DEBUG
   2131 			aprint_debug_dev(sc->sc_dev, "link up: full duplex\n");
   2132 #endif
   2133 		} else if (v & GEM_MII_ANEG_HLF_DUPLX) {
   2134 			sc->sc_mii.mii_media_active |= IFM_HDX;
   2135 #ifdef GEM_DEBUG
   2136 			aprint_debug_dev(sc->sc_dev, "link up: half duplex\n");
   2137 #endif
   2138 		} else {
   2139 #ifdef GEM_DEBUG
   2140 			aprint_debug_dev(sc->sc_dev, "duplex mismatch\n");
   2141 #endif
   2142 		}
   2143 		gem_statuschange(sc);
   2144 	} else {
   2145 		if ((sc->sc_flags & GEM_LINK) == 0) {
   2146 			return 1;
   2147 		}
   2148 		sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE;
   2149 		sc->sc_mii.mii_media_status = IFM_AVALID;
   2150 #ifdef GEM_DEBUG
   2151 			aprint_debug_dev(sc->sc_dev, "link down\n");
   2152 #endif
   2153 		gem_statuschange(sc);
   2154 
   2155 		/* Start the 10 second timer */
   2156 		callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc);
   2157 	}
   2158 	return 1;
   2159 }
   2160 
   2161 
   2162 
   2163 int
   2164 gem_intr(void *v)
   2165 {
   2166 	struct gem_softc *sc = v;
   2167 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2168 	bus_space_tag_t t = sc->sc_bustag;
   2169 	bus_space_handle_t h = sc->sc_h1;
   2170 	u_int32_t status;
   2171 	int r = 0;
   2172 #ifdef GEM_DEBUG
   2173 	char bits[128];
   2174 #endif
   2175 
   2176 	/* XXX We should probably mask out interrupts until we're done */
   2177 
   2178 	sc->sc_ev_intr.ev_count++;
   2179 
   2180 	status = bus_space_read_4(t, h, GEM_STATUS);
   2181 #ifdef GEM_DEBUG
   2182 	snprintb(bits, sizeof(bits), GEM_INTR_BITS, status);
   2183 #endif
   2184 	DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n",
   2185 		device_xname(sc->sc_dev), (status >> 19), bits));
   2186 
   2187 
   2188 	if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
   2189 		r |= gem_eint(sc, status);
   2190 
   2191 	/* We don't bother with GEM_INTR_TX_DONE */
   2192 	if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) {
   2193 		GEM_COUNTER_INCR(sc, sc_ev_txint);
   2194 		r |= gem_tint(sc);
   2195 	}
   2196 
   2197 	if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) {
   2198 		GEM_COUNTER_INCR(sc, sc_ev_rxint);
   2199 		r |= gem_rint(sc);
   2200 	}
   2201 
   2202 	/* We should eventually do more than just print out error stats. */
   2203 	if (status & GEM_INTR_TX_MAC) {
   2204 		int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS);
   2205 		if (txstat & ~GEM_MAC_TX_XMIT_DONE)
   2206 			printf("%s: MAC tx fault, status %x\n",
   2207 			    device_xname(sc->sc_dev), txstat);
   2208 		if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
   2209 			gem_init(ifp);
   2210 	}
   2211 	if (status & GEM_INTR_RX_MAC) {
   2212 		int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS);
   2213 		/*
   2214 		 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
   2215 		 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
   2216 		 * silicon bug so handle them silently.  So if we detect
   2217 		 * an RX FIFO overflow, we fire off a timer, and check
   2218 		 * whether we're still making progress by looking at the
   2219 		 * RX FIFO write and read pointers.
   2220 		 */
   2221 		if (rxstat & GEM_MAC_RX_OVERFLOW) {
   2222 			ifp->if_ierrors++;
   2223 			aprint_error_dev(sc->sc_dev,
   2224 			    "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
   2225 			sc->sc_rx_fifo_wr_ptr =
   2226 				bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR);
   2227 			sc->sc_rx_fifo_rd_ptr =
   2228 				bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR);
   2229 			callout_schedule(&sc->sc_rx_watchdog, 400);
   2230 		} else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
   2231 			printf("%s: MAC rx fault, status 0x%02x\n",
   2232 			    device_xname(sc->sc_dev), rxstat);
   2233 	}
   2234 	if (status & GEM_INTR_PCS) {
   2235 		r |= gem_pint(sc);
   2236 	}
   2237 
   2238 /* Do we need to do anything with these?
   2239 	if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
   2240 		status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS);
   2241 		if ((status2 & GEM_MAC_PAUSED) != 0)
   2242 			aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n",
   2243 			    GEM_MAC_PAUSE_TIME(status2));
   2244 		if ((status2 & GEM_MAC_PAUSE) != 0)
   2245 			aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n");
   2246 		if ((status2 & GEM_MAC_RESUME) != 0)
   2247 			aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n");
   2248 	}
   2249 	if ((status & GEM_INTR_MIF) != 0)
   2250 		aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n");
   2251 */
   2252 	rnd_add_uint32(&sc->rnd_source, status);
   2253 	return (r);
   2254 }
   2255 
   2256 void
   2257 gem_rx_watchdog(void *arg)
   2258 {
   2259 	struct gem_softc *sc = arg;
   2260 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2261 	bus_space_tag_t t = sc->sc_bustag;
   2262 	bus_space_handle_t h = sc->sc_h1;
   2263 	u_int32_t rx_fifo_wr_ptr;
   2264 	u_int32_t rx_fifo_rd_ptr;
   2265 	u_int32_t state;
   2266 
   2267 	if ((ifp->if_flags & IFF_RUNNING) == 0) {
   2268 		aprint_error_dev(sc->sc_dev, "receiver not running\n");
   2269 		return;
   2270 	}
   2271 
   2272 	rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR);
   2273 	rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR);
   2274 	state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE);
   2275 	if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW &&
   2276 	    ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) ||
   2277 	     ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) &&
   2278 	      (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr))))
   2279 	{
   2280 		/*
   2281 		 * The RX state machine is still in overflow state and
   2282 		 * the RX FIFO write and read pointers seem to be
   2283 		 * stuck.  Whack the chip over the head to get things
   2284 		 * going again.
   2285 		 */
   2286 		aprint_error_dev(sc->sc_dev,
   2287 		    "receiver stuck in overflow, resetting\n");
   2288 		gem_init(ifp);
   2289 	} else {
   2290 		if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) {
   2291 			aprint_error_dev(sc->sc_dev,
   2292 				"rx_watchdog: not in overflow state: 0x%x\n",
   2293 				state);
   2294 		}
   2295 		if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) {
   2296 			aprint_error_dev(sc->sc_dev,
   2297 				"rx_watchdog: wr & rd ptr different\n");
   2298 		}
   2299 		if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) {
   2300 			aprint_error_dev(sc->sc_dev,
   2301 				"rx_watchdog: wr pointer != saved\n");
   2302 		}
   2303 		if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) {
   2304 			aprint_error_dev(sc->sc_dev,
   2305 				"rx_watchdog: rd pointer != saved\n");
   2306 		}
   2307 		aprint_error_dev(sc->sc_dev, "resetting anyway\n");
   2308 		gem_init(ifp);
   2309 	}
   2310 }
   2311 
   2312 void
   2313 gem_watchdog(struct ifnet *ifp)
   2314 {
   2315 	struct gem_softc *sc = ifp->if_softc;
   2316 
   2317 	DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
   2318 		"GEM_MAC_RX_CONFIG %x\n",
   2319 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG),
   2320 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS),
   2321 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG)));
   2322 
   2323 	log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev));
   2324 	++ifp->if_oerrors;
   2325 
   2326 	/* Try to get more packets going. */
   2327 	gem_init(ifp);
   2328 	gem_start(ifp);
   2329 }
   2330 
   2331 /*
   2332  * Initialize the MII Management Interface
   2333  */
   2334 void
   2335 gem_mifinit(struct gem_softc *sc)
   2336 {
   2337 	bus_space_tag_t t = sc->sc_bustag;
   2338 	bus_space_handle_t mif = sc->sc_h1;
   2339 
   2340 	/* Configure the MIF in frame mode */
   2341 	sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
   2342 	sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
   2343 	bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
   2344 }
   2345 
   2346 /*
   2347  * MII interface
   2348  *
   2349  * The GEM MII interface supports at least three different operating modes:
   2350  *
   2351  * Bitbang mode is implemented using data, clock and output enable registers.
   2352  *
   2353  * Frame mode is implemented by loading a complete frame into the frame
   2354  * register and polling the valid bit for completion.
   2355  *
   2356  * Polling mode uses the frame register but completion is indicated by
   2357  * an interrupt.
   2358  *
   2359  */
   2360 static int
   2361 gem_mii_readreg(device_t self, int phy, int reg)
   2362 {
   2363 	struct gem_softc *sc = device_private(self);
   2364 	bus_space_tag_t t = sc->sc_bustag;
   2365 	bus_space_handle_t mif = sc->sc_h1;
   2366 	int n;
   2367 	u_int32_t v;
   2368 
   2369 #ifdef GEM_DEBUG1
   2370 	if (sc->sc_debug)
   2371 		printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg);
   2372 #endif
   2373 
   2374 	/* Construct the frame command */
   2375 	v = (reg << GEM_MIF_REG_SHIFT)	| (phy << GEM_MIF_PHY_SHIFT) |
   2376 		GEM_MIF_FRAME_READ;
   2377 
   2378 	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
   2379 	for (n = 0; n < 100; n++) {
   2380 		DELAY(1);
   2381 		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
   2382 		if (v & GEM_MIF_FRAME_TA0)
   2383 			return (v & GEM_MIF_FRAME_DATA);
   2384 	}
   2385 
   2386 	printf("%s: mii_read timeout\n", device_xname(sc->sc_dev));
   2387 	return (0);
   2388 }
   2389 
   2390 static void
   2391 gem_mii_writereg(device_t self, int phy, int reg, int val)
   2392 {
   2393 	struct gem_softc *sc = device_private(self);
   2394 	bus_space_tag_t t = sc->sc_bustag;
   2395 	bus_space_handle_t mif = sc->sc_h1;
   2396 	int n;
   2397 	u_int32_t v;
   2398 
   2399 #ifdef GEM_DEBUG1
   2400 	if (sc->sc_debug)
   2401 		printf("gem_mii_writereg: PHY %d reg %d val %x\n",
   2402 			phy, reg, val);
   2403 #endif
   2404 
   2405 	/* Construct the frame command */
   2406 	v = GEM_MIF_FRAME_WRITE			|
   2407 	    (phy << GEM_MIF_PHY_SHIFT)		|
   2408 	    (reg << GEM_MIF_REG_SHIFT)		|
   2409 	    (val & GEM_MIF_FRAME_DATA);
   2410 
   2411 	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
   2412 	for (n = 0; n < 100; n++) {
   2413 		DELAY(1);
   2414 		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
   2415 		if (v & GEM_MIF_FRAME_TA0)
   2416 			return;
   2417 	}
   2418 
   2419 	printf("%s: mii_write timeout\n", device_xname(sc->sc_dev));
   2420 }
   2421 
   2422 static void
   2423 gem_mii_statchg(struct ifnet *ifp)
   2424 {
   2425 	struct gem_softc *sc = ifp->if_softc;
   2426 #ifdef GEM_DEBUG
   2427 	int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
   2428 #endif
   2429 
   2430 #ifdef GEM_DEBUG
   2431 	if (sc->sc_debug)
   2432 		printf("gem_mii_statchg: status change: phy = %d\n",
   2433 			sc->sc_phys[instance]);
   2434 #endif
   2435 	gem_statuschange(sc);
   2436 }
   2437 
   2438 /*
   2439  * Common status change for gem_mii_statchg() and gem_pint()
   2440  */
   2441 void
   2442 gem_statuschange(struct gem_softc* sc)
   2443 {
   2444 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2445 	bus_space_tag_t t = sc->sc_bustag;
   2446 	bus_space_handle_t mac = sc->sc_h1;
   2447 	int gigabit;
   2448 	u_int32_t rxcfg, txcfg, v;
   2449 
   2450 	if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 &&
   2451 	    IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE)
   2452 		sc->sc_flags |= GEM_LINK;
   2453 	else
   2454 		sc->sc_flags &= ~GEM_LINK;
   2455 
   2456 	if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000))
   2457 		gigabit = 1;
   2458 	else
   2459 		gigabit = 0;
   2460 
   2461 	/*
   2462 	 * The configuration done here corresponds to the steps F) and
   2463 	 * G) and as far as enabling of RX and TX MAC goes also step H)
   2464 	 * of the initialization sequence outlined in section 3.2.1 of
   2465 	 * the GEM Gigabit Ethernet ASIC Specification.
   2466 	 */
   2467 
   2468 	rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG);
   2469 	rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE);
   2470 	txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
   2471 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
   2472 		txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
   2473 	else if (gigabit) {
   2474 		rxcfg |= GEM_MAC_RX_CARR_EXTEND;
   2475 		txcfg |= GEM_MAC_RX_CARR_EXTEND;
   2476 	}
   2477 	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
   2478 	bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4,
   2479 	    BUS_SPACE_BARRIER_WRITE);
   2480 	if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
   2481 		aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n");
   2482 	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg);
   2483 	bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0);
   2484 	bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4,
   2485 	    BUS_SPACE_BARRIER_WRITE);
   2486 	if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
   2487 		aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n");
   2488 	bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg);
   2489 
   2490 	v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) &
   2491 	    ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
   2492 	bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v);
   2493 
   2494 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 &&
   2495 	    gigabit != 0)
   2496 		bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME,
   2497 		    GEM_MAC_SLOT_TIME_CARR_EXTEND);
   2498 	else
   2499 		bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME,
   2500 		    GEM_MAC_SLOT_TIME_NORMAL);
   2501 
   2502 	/* XIF Configuration */
   2503 	if (sc->sc_flags & GEM_LINK)
   2504 		v = GEM_MAC_XIF_LINK_LED;
   2505 	else
   2506 		v = 0;
   2507 	v |= GEM_MAC_XIF_TX_MII_ENA;
   2508 
   2509 	/* If an external transceiver is connected, enable its MII drivers */
   2510 	sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
   2511 	if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) {
   2512 		if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
   2513 			if (gigabit)
   2514 				v |= GEM_MAC_XIF_GMII_MODE;
   2515 			else
   2516 				v &= ~GEM_MAC_XIF_GMII_MODE;
   2517 		} else
   2518 			/* Internal MII needs buf enable */
   2519 			v |= GEM_MAC_XIF_MII_BUF_ENA;
   2520 		/* MII needs echo disable if half duplex. */
   2521 		if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
   2522 			/* turn on full duplex LED */
   2523 			v |= GEM_MAC_XIF_FDPLX_LED;
   2524 		else
   2525 			/* half duplex -- disable echo */
   2526 			v |= GEM_MAC_XIF_ECHO_DISABL;
   2527 	} else {
   2528 		if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
   2529 			v |= GEM_MAC_XIF_FDPLX_LED;
   2530 		v |= GEM_MAC_XIF_GMII_MODE;
   2531 	}
   2532 	bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
   2533 
   2534 	if ((ifp->if_flags & IFF_RUNNING) != 0 &&
   2535 	    (sc->sc_flags & GEM_LINK) != 0) {
   2536 		bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG,
   2537 		    txcfg | GEM_MAC_TX_ENABLE);
   2538 		bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG,
   2539 		    rxcfg | GEM_MAC_RX_ENABLE);
   2540 	}
   2541 }
   2542 
   2543 int
   2544 gem_ser_mediachange(struct ifnet *ifp)
   2545 {
   2546 	struct gem_softc *sc = ifp->if_softc;
   2547 	u_int s, t;
   2548 
   2549 	if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER)
   2550 		return EINVAL;
   2551 
   2552 	s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media);
   2553 	if (s == IFM_AUTO) {
   2554 		if (sc->sc_mii_media != s) {
   2555 #ifdef GEM_DEBUG
   2556 			aprint_debug_dev(sc->sc_dev, "setting media to auto\n");
   2557 #endif
   2558 			sc->sc_mii_media = s;
   2559 			if (ifp->if_flags & IFF_UP) {
   2560 				gem_pcs_stop(sc, 0);
   2561 				gem_pcs_start(sc);
   2562 			}
   2563 		}
   2564 		return 0;
   2565 	}
   2566 	if (s == IFM_1000_SX) {
   2567 		t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media);
   2568 		if (t == IFM_FDX || t == IFM_HDX) {
   2569 			if (sc->sc_mii_media != t) {
   2570 				sc->sc_mii_media = t;
   2571 #ifdef GEM_DEBUG
   2572 				aprint_debug_dev(sc->sc_dev,
   2573 				    "setting media to 1000baseSX-%s\n",
   2574 				    t == IFM_FDX ? "FDX" : "HDX");
   2575 #endif
   2576 				if (ifp->if_flags & IFF_UP) {
   2577 					gem_pcs_stop(sc, 0);
   2578 					gem_pcs_start(sc);
   2579 				}
   2580 			}
   2581 			return 0;
   2582 		}
   2583 	}
   2584 	return EINVAL;
   2585 }
   2586 
   2587 void
   2588 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   2589 {
   2590 	struct gem_softc *sc = ifp->if_softc;
   2591 
   2592 	if ((ifp->if_flags & IFF_UP) == 0)
   2593 		return;
   2594 	ifmr->ifm_active = sc->sc_mii.mii_media_active;
   2595 	ifmr->ifm_status = sc->sc_mii.mii_media_status;
   2596 }
   2597 
   2598 static int
   2599 gem_ifflags_cb(struct ethercom *ec)
   2600 {
   2601 	struct ifnet *ifp = &ec->ec_if;
   2602 	struct gem_softc *sc = ifp->if_softc;
   2603 	int change = ifp->if_flags ^ sc->sc_if_flags;
   2604 
   2605 	if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0)
   2606 		return ENETRESET;
   2607 	else if ((change & IFF_PROMISC) != 0)
   2608 		gem_setladrf(sc);
   2609 	return 0;
   2610 }
   2611 
   2612 /*
   2613  * Process an ioctl request.
   2614  */
   2615 int
   2616 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data)
   2617 {
   2618 	struct gem_softc *sc = ifp->if_softc;
   2619 	int s, error = 0;
   2620 
   2621 	s = splnet();
   2622 
   2623 	if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
   2624 		error = 0;
   2625 		if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
   2626 			;
   2627 		else if (ifp->if_flags & IFF_RUNNING) {
   2628 			/*
   2629 			 * Multicast list has changed; set the hardware filter
   2630 			 * accordingly.
   2631 			 */
   2632 			gem_setladrf(sc);
   2633 		}
   2634 	}
   2635 
   2636 	/* Try to get things going again */
   2637 	if (ifp->if_flags & IFF_UP)
   2638 		gem_start(ifp);
   2639 	splx(s);
   2640 	return (error);
   2641 }
   2642 
   2643 static void
   2644 gem_inten(struct gem_softc *sc)
   2645 {
   2646 	bus_space_tag_t t = sc->sc_bustag;
   2647 	bus_space_handle_t h = sc->sc_h1;
   2648 	uint32_t v;
   2649 
   2650 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
   2651 		v = GEM_INTR_PCS;
   2652 	else
   2653 		v = GEM_INTR_MIF;
   2654 	bus_space_write_4(t, h, GEM_INTMASK,
   2655 		      ~(GEM_INTR_TX_INTME |
   2656 			GEM_INTR_TX_EMPTY |
   2657 			GEM_INTR_TX_MAC |
   2658 			GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF|
   2659 			GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL|
   2660 			GEM_INTR_BERR | v));
   2661 }
   2662 
   2663 bool
   2664 gem_resume(device_t self, const pmf_qual_t *qual)
   2665 {
   2666 	struct gem_softc *sc = device_private(self);
   2667 
   2668 	gem_inten(sc);
   2669 
   2670 	return true;
   2671 }
   2672 
   2673 bool
   2674 gem_suspend(device_t self, const pmf_qual_t *qual)
   2675 {
   2676 	struct gem_softc *sc = device_private(self);
   2677 	bus_space_tag_t t = sc->sc_bustag;
   2678 	bus_space_handle_t h = sc->sc_h1;
   2679 
   2680 	bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0);
   2681 
   2682 	return true;
   2683 }
   2684 
   2685 bool
   2686 gem_shutdown(device_t self, int howto)
   2687 {
   2688 	struct gem_softc *sc = device_private(self);
   2689 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2690 
   2691 	gem_stop(ifp, 1);
   2692 
   2693 	return true;
   2694 }
   2695 
   2696 /*
   2697  * Set up the logical address filter.
   2698  */
   2699 void
   2700 gem_setladrf(struct gem_softc *sc)
   2701 {
   2702 	struct ethercom *ec = &sc->sc_ethercom;
   2703 	struct ifnet *ifp = &ec->ec_if;
   2704 	struct ether_multi *enm;
   2705 	struct ether_multistep step;
   2706 	bus_space_tag_t t = sc->sc_bustag;
   2707 	bus_space_handle_t h = sc->sc_h1;
   2708 	u_int32_t crc;
   2709 	u_int32_t hash[16];
   2710 	u_int32_t v;
   2711 	int i;
   2712 
   2713 	/* Get current RX configuration */
   2714 	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
   2715 
   2716 	/*
   2717 	 * Turn off promiscuous mode, promiscuous group mode (all multicast),
   2718 	 * and hash filter.  Depending on the case, the right bit will be
   2719 	 * enabled.
   2720 	 */
   2721 	v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
   2722 	    GEM_MAC_RX_PROMISC_GRP);
   2723 
   2724 	if ((ifp->if_flags & IFF_PROMISC) != 0) {
   2725 		/* Turn on promiscuous mode */
   2726 		v |= GEM_MAC_RX_PROMISCUOUS;
   2727 		ifp->if_flags |= IFF_ALLMULTI;
   2728 		goto chipit;
   2729 	}
   2730 
   2731 	/*
   2732 	 * Set up multicast address filter by passing all multicast addresses
   2733 	 * through a crc generator, and then using the high order 8 bits as an
   2734 	 * index into the 256 bit logical address filter.  The high order 4
   2735 	 * bits selects the word, while the other 4 bits select the bit within
   2736 	 * the word (where bit 0 is the MSB).
   2737 	 */
   2738 
   2739 	/* Clear hash table */
   2740 	memset(hash, 0, sizeof(hash));
   2741 
   2742 	ETHER_FIRST_MULTI(step, ec, enm);
   2743 	while (enm != NULL) {
   2744 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   2745 			/*
   2746 			 * We must listen to a range of multicast addresses.
   2747 			 * For now, just accept all multicasts, rather than
   2748 			 * trying to set only those filter bits needed to match
   2749 			 * the range.  (At this time, the only use of address
   2750 			 * ranges is for IP multicast routing, for which the
   2751 			 * range is big enough to require all bits set.)
   2752 			 * XXX should use the address filters for this
   2753 			 */
   2754 			ifp->if_flags |= IFF_ALLMULTI;
   2755 			v |= GEM_MAC_RX_PROMISC_GRP;
   2756 			goto chipit;
   2757 		}
   2758 
   2759 		/* Get the LE CRC32 of the address */
   2760 		crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo));
   2761 
   2762 		/* Just want the 8 most significant bits. */
   2763 		crc >>= 24;
   2764 
   2765 		/* Set the corresponding bit in the filter. */
   2766 		hash[crc >> 4] |= 1 << (15 - (crc & 15));
   2767 
   2768 		ETHER_NEXT_MULTI(step, enm);
   2769 	}
   2770 
   2771 	v |= GEM_MAC_RX_HASH_FILTER;
   2772 	ifp->if_flags &= ~IFF_ALLMULTI;
   2773 
   2774 	/* Now load the hash table into the chip (if we are using it) */
   2775 	for (i = 0; i < 16; i++) {
   2776 		bus_space_write_4(t, h,
   2777 		    GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
   2778 		    hash[i]);
   2779 	}
   2780 
   2781 chipit:
   2782 	sc->sc_if_flags = ifp->if_flags;
   2783 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
   2784 }
   2785